TUNNEL JUNCTION PATTERNING FOR CONTROLLING OPTICAL AND CURRENT CONFINEMENT IN A VERTICAL-CAVITY SURFACE-EMITTING LASER

    公开(公告)号:US20240380184A1

    公开(公告)日:2024-11-14

    申请号:US18144984

    申请日:2023-05-09

    Abstract: Some embodiments of the present invention are directed to a tunnel junction for a vertical-cavity surface-emitting laser (VCSEL) that controls optical and current confinement within the VCSEL. The tunnel junction may define an electrical current injection area and an optical aperture for the VCSEL and may include a heavily p++ doped p-type material and a heavily n++ doped n-type material disposed on the p-type material. At least a portion of the outer edges of the n-type material are etched such that the n-type material has a cross-sectional area that is less than a cross-sectional area of the p-type material. By removing a portion of n-type material near the outer edge of the tunnel junction, a sloped effective refractive index is formed, and an effective area of the tunnel junction is changed, which increases the overlap of the current density and the optical field of the VCSEL.

    SYSTEMS AND METHODS OF MESSAGE-BASED PACKETS

    公开(公告)号:US20240372923A1

    公开(公告)日:2024-11-07

    申请号:US18143411

    申请日:2023-05-04

    Abstract: A system for transmitting data is described, among other things. An illustrative system is disclosed to include one or more circuits to perform transmitting message-based data over packets. The circuits are capable of identifying a first message, transmitting a first portion of the first message in a first packet, the first packet including a bit indicating the first packet is message-based, and transmitting an end portion of the first message in a second packet, the second packet including a first bit indicating the second packet is message-based and a second bit indicating the second packet comprises the end portion of the first message.

    SECURE AND SCALABLE CHIP CONTROL REGISTER FABRIC

    公开(公告)号:US20240370579A1

    公开(公告)日:2024-11-07

    申请号:US18142968

    申请日:2023-05-03

    Abstract: A system, circuit, and method are described, among other things. An illustrative system is disclosed to include a processor and a memory storing data for processing by the processor. The data, when processed, causes the processor to receive an initiator message comprising a request to access one or more registers of a plurality of registers, determine that the initiator message corresponds to an entry of a privilege access table, determine a configured level of access control for the initiator message to access the one or more requested registers based at least in part on a group mapping table, and provide a level of access to the one or more requested registers corresponding to the received initiator message based on the initiator message corresponding to the entry of the privilege access table and based, at least in part, on the determined configured level of access control.

    Efficient montgomery multiplier
    44.
    发明授权

    公开(公告)号:US12131132B2

    公开(公告)日:2024-10-29

    申请号:US17180993

    申请日:2021-02-22

    CPC classification number: G06F7/728

    Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.

    QUANTUM DEVICES AND MEMORY STRUCTURES FOR QUANTUM METROLOGY

    公开(公告)号:US20240354617A1

    公开(公告)日:2024-10-24

    申请号:US18137755

    申请日:2023-04-21

    CPC classification number: G06N10/40 G06N10/20

    Abstract: Quantum systems, devices, and methods are described herein that enable quantum metrology. An example quantum device includes a first quantum measurement module operably coupled with a first quantum system. The first quantum measurement module applies one or more measurements to the first quantum system and obtains first information associated with the first quantum system based on the one or more measurements. The quantum device further includes a first quantum memory structure operably coupled with the first quantum measurement module. A coherence time window associated with the first quantum memory structure is greater than a coherence time window time associated with the first quantum system. The quantum devices and associated memory structures provide a new methodology for a quantum metrology system.

    SIGNAL DISTORTION CORRECTION WITH TIME-TO-DIGITAL CONVERTER (TDC)

    公开(公告)号:US20240348417A1

    公开(公告)日:2024-10-17

    申请号:US18751029

    申请日:2024-06-21

    Inventor: Igal Kushnir

    CPC classification number: H04L7/0016 G04F10/005 H03K3/017

    Abstract: A system includes a first device coupled with a link which transmits a signal having a repeating pattern, and a second device coupled with the link. The second device is to receive the signal, generate one or more delayed signals from the signal, determine a first duration of a first portion of the repeating pattern and a second duration of a second portion of the repeating pattern using the one or more delayed signals, and adjust a current duty cycle of the signal based on the first duration and the second duration.

    Real-time performance optimization of a packet network

    公开(公告)号:US20240323123A1

    公开(公告)日:2024-09-26

    申请号:US18310550

    申请日:2023-05-02

    CPC classification number: H04L47/12 H04L41/22 H04L43/08

    Abstract: A communication system (20) includes a plurality of Network Interface Controllers (NICs) (32) and one or more processors (28, 62, 64). The plurality of NICs are to connect multiple hosts to a communication network, the NICs supporting a configurable Congestion Control (CC) scheme (80) selected from among multiple CC schemes. The one or more processors are coupled to the communication network, and are to receive performance indicators indicative of congestion states occurring in the communication network due to communication of the hosts with one another over the communication network, the performance indicators being associated with respective times of occurrence, select respective CC schemes for one or more of the NICs based on the performance indicators and corresponding times of occurrence, and provision the selected CC schemes in the one or more of the NICs.

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