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公开(公告)号：US09270291B1
公开(公告)日：2016-02-23
申请号：US14662001
申请日：2015-03-18
申请人： Broadcom Corporation
CPC分类号： H03M1/121 , H03M1/0836 , H03M1/1028 , H03M1/1215 , H03M1/1245 , H04B17/21 , H04L7/0004
摘要： Methods and apparatuses are described for timing skew mitigation in time-interleaved ADCs (TI-ADCs) that may be performed for any receive signal without any special signals during blind initialization, which may be followed by background calibration. The same gain/skew calibration metrics may be applied to baud sampled and oversampled systems, including wideband receivers and regardless of any modulation, by applying a timing or frequency offset to non-stationary sampled signals during initial training. Skew mitigation is low latency, low power, low area, noise tolerant and scalable. Digital estimation may be implemented with accumulators and multipliers while analog calibration may be implemented with adjustable delays. DC and gain offsets may be calibrated before skew calibration. The slope of the correlation function between adjacent samples may be used to move a timing skew estimate stochastically at a low adaptive rate until the skew algorithm converges.
摘要翻译： 描述了用于在盲初始化期间可以对任何接收信号执行任何特殊信号的时间交织ADC（TI-ADC）中的定时偏移缓解的方法和装置，其可以在背景校准之后进行。 相同的增益/偏斜校准度量可以应用于波特率采样和过采样系统，包括宽带接收机，无论任何调制，通过在初始训练期间对非平稳采样信号应用定时或频率偏移。 倾斜减轻是低延迟，低功率，低面积，噪声容限和可扩展性。 数字估计可以用累加器和乘法器来实现，而模拟校准可以用可调延迟来实现。 在校准偏差之前可以校准直流和增益偏移。 相邻样本之间的相关函数的斜率可以用于以低自适应速率随机移动定时偏差估计，直到偏斜算法收敛。
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42.发明申请Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation 有权时间交错模数转换器时序不匹配估计和补偿的方法和系统公开(公告)号：US20160043731A1
公开(公告)日：2016-02-11
申请号：US14920699
申请日：2015-10-22
申请人： Maxlinear, Inc.
发明人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
CPC分类号： H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
摘要翻译： 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 以及通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
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43.发明申请公开(公告)号：US20160006447A1
公开(公告)日：2016-01-07
申请号：US14769914
申请日：2014-03-07
申请人： Anacatum Design AB
发明人： Rolf SUNDBLAD
CPC分类号： H03M1/1004 , H03M1/1057 , H03M1/121 , H03M1/1215 , H03M1/1245
摘要： A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.
摘要翻译： 操作用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器的方法包括针对组成模数转换器阵列的至少一些激活的每一个 转换器，定义第一组和第二组组成模数转换器，将第一组的每个模数转换器的模拟输入馈送到不完整测量的参考值，并使每个模数转换器 第一组具有一个定时信号，将第二组的模拟 - 数字转换器的模拟输入馈送到模拟输入信号，以在数字输出端产生中间组成数字输出信号，并为每个模拟 - 具有定时信号之一的第二组的数模转换器，其中没有定时信号用于对第二组的模数转换器中的两个或更多个进行定时。
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公开(公告)号：US20150341043A1
公开(公告)日：2015-11-26
申请号：US14817645
申请日：2015-08-04
发明人： Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
CPC分类号： H03M1/0634 , H03M1/002 , H03M1/0617 , H03M1/1009 , H03M1/12 , H03M1/1215 , H03M1/1225
摘要： An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
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公开(公告)号：US09184737B1
公开(公告)日：2015-11-10
申请号：US14332106
申请日：2014-07-15
申请人： Broadcom Corporation
CPC分类号： H04B17/21 , H03K5/135 , H03M1/1023 , H03M1/1215 , H03M1/1245 , H04L7/0012
摘要： A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.
摘要翻译： 一种设备包括进程减轻时序（PMT）电路。 PMT电路允许调整时钟信号，同时补偿PMT电路内的过程变化。 PMT电路可以包括过程减缓缓冲器（PMB）电路。 PMB电路可以利用复制电路和经校准的电阻来产生校准偏置电压。 校准的偏置电压可用于驱动元件缓冲器电路以产生校准的电流响应。 校准的电流响应可以对应于组件缓冲器电路的选择的输出阻抗。 选择输出阻抗可以与可变电容一起使用，以独立于PMT电路内的过程变化的方式调整时钟信号。
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46.发明授权Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权时间交错模数转换器定时失配估计和补偿的方法和系统公开(公告)号：US09172386B2
公开(公告)日：2015-10-27
申请号：US14590250
申请日：2015-01-06
申请人： Maxlinear, Inc.
发明人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
CPC分类号： H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
摘要翻译： 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
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47.发明授权公开(公告)号：US09166608B1
公开(公告)日：2015-10-20
申请号：US14731471
申请日：2015-06-05
申请人： IMEC VZW
发明人： Kazuaki Deguchi , Bob Verbruggen , Jan Craninckx
CPC分类号： H03M1/0604 , H03M1/00 , H03M1/002 , H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/1215 , H03M1/14 , H03M1/468 , H03M2201/4233
摘要： Methods and devices herein relate to a method for estimating bandwidth mismatch in a time-interleaved A/D converter. An example method includes precharging terminals of capacitors to a first state in each channel of a plurality of channels and sampling a reference analog input voltage signal (Vref) applied via a first switchable path whereby the sampled input voltage signal is received at first terminals of the capacitors. The method further includes setting the second terminals of each channel to a second state. The method also includes applying the reference analog input voltage signal to the first terminals via a second switchable path, and thereby creating on the first terminals a non-zero settling error. The method additionally includes quantizing the settling error to obtain an estimate of the non-zero settling error. The method yet further includes comparing the estimates of the non-zero settling errors and deriving an estimation of the bandwidth mismatch.
摘要翻译： 这里的方法和装置涉及用于估计时间交织的A / D转换器中的带宽不匹配的方法。 示例性方法包括：在多个通道的每个通道中将电容器的端子预充电到第一状态，并对通过第一可切换路径施加的参考模拟输入电压信号（Vref）进行采样，由此在第一端子处接收采样的输入电压信号 电容器 该方法还包括将每个信道的第二终端设置为第二状态。 该方法还包括经由第二可切换路径将参考模拟输入电压信号施加到第一端子，从而在第一端子上产生非零稳定误差。 该方法另外包括量化沉降误差以获得非零建立误差的估计。 该方法还包括比较非零建立误差的估计并导出带宽不匹配的估计。
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公开(公告)号：US20150280725A1
公开(公告)日：2015-10-01
申请号：US14322514
申请日：2014-07-02
CPC分类号： H03M1/38 , H03M1/0675 , H03M1/0678 , H03M1/0836 , H03M1/1215 , H03M1/124 , H03M1/14
摘要： Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
摘要翻译： 将模拟信号转换为数字信号的系统和方法。 参考切片与多个活动切片中的每一个相关联，以平衡每个活动切片内的有源采样轨道和保持放大器上的负载。 或者，参考切片被分割成具有由多个部分参考切片共享的参考ADC的部分，每个部分参考切片具有部分参考输入模块。
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公开(公告)号：US09143149B1
公开(公告)日：2015-09-22
申请号：US14322514
申请日：2014-07-02
CPC分类号： H03M1/38 , H03M1/0675 , H03M1/0678 , H03M1/0836 , H03M1/1215 , H03M1/124 , H03M1/14
摘要： Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
摘要翻译： 将模拟信号转换为数字信号的系统和方法。 参考切片与多个活动切片中的每一个相关联，以平衡每个活动切片内的有源采样轨道和保持放大器上的负载。 或者，参考切片被分割成具有由多个部分参考切片共享的参考ADC的部分，每个部分参考切片具有部分参考输入模块。
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公开(公告)号：US20150244547A1
公开(公告)日：2015-08-27
申请号：US14634176
申请日：2015-02-27
申请人： IMEC VZW , Universiteit Gent
CPC分类号： H04L25/4917 , H03M1/1215 , H03M1/361 , H04B10/60
摘要： Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values. The circuitry also includes N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n−1) sample-and-hold circuits for generating at least one binary signal having a period N*T.
摘要翻译： 用于将多电平信号转换成具有周期T并且包括n个信号电平的至少一个二进制信号的电路包括比较和分离电路，其配置用于将多电平信号的值与（n-1）个不同参考值 并且具有N组（n-1）个输出端子，用于输出指示多电平信号的值是否低于或高于（n-1）个参考值的N组（n-1）个输出信号。 电路还包括具有输入和输出的N组（n-1）采样保持电路，并被配置为在时钟周期N * T下工作，其中每个输出端连接到采样保持电路的输入端， 保持电路。 此外，电路包括连接到N组（n-1）个采样和保持电路的输出的逻辑电路，用于产生具有周期N * T的至少一个二进制信号。
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