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公开(公告)号：US20140253352A1
公开(公告)日：2014-09-11
申请号：US14203052
申请日：2014-03-10
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Takashi OSHIMA , Tatsuji MATSUURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA
IPC: H03M1/06
CPC classification number: H03M1/1245 , H03M1/002 , H03M1/0609 , H03M1/0639 , H03M1/1038 , H03M1/109 , H03M1/14 , H03M1/38 , H03M1/44 , H03M1/46 , H03M1/56
Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
Abstract translation: 在小区域中实现了作为电荷共享型并进行逐次逼近的数字校正型A / D转换器。 A / D转换器配置有作为电荷共享型的A / D转换单元并执行逐次逼近，数字校正单元接收A / D转换单元的数字输出并对数字输出执行数字校正， 以及保持测试信号的保持单元。 来自保持单元的公共值的测试信号在第一周期和第二周期中被输入到A / D转换单元。 基于第一周期中的数字校正单元的数字校正结果和第二周期中的数字校正单元的数字校正结果来计算数字校正单元的A / D转换校正系数。
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公开(公告)号：US20170045578A1
公开(公告)日：2017-02-16
申请号：US15218006
申请日：2016-07-23
Applicant: Renesas Electronics Corporation
Inventor： Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA , Takashi OSHIMA
IPC: G01R31/3163
CPC classification number: G01R35/00 , G01R19/2509 , H03M1/1038 , H03M1/1076 , H03M1/468
Abstract: The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.
Abstract translation: 本发明提供能够检测构成模拟电路的元件之间的过度变化的故障的半导体器件和故障检测方法。 根据实施例，半导体器件1包括：AD转换器11; 数字辅助电路12，其对与由AD转换器11处理的模拟信号Ain相对应的数字信号Do的错误进行校正; 以及故障检测电路13，其基于数字辅助电路的校正量来检测AD转换器11是否具有故障。 因此，半导体器件1能够检测作为失败的构成AD转换器11的元件之间的过度变化。
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公开(公告)号：US20150381192A1
公开(公告)日：2015-12-31
申请号：US14750242
申请日：2015-06-25
Applicant: Renesas Electronics Corporation
Inventor： Takaya YAMAMOTO , Hideo NAKANE , Keisuke KIMURA , Yuichi OKUDA , Takashi OSHIMA
CPC classification number: H03M1/002 , H03M1/0609 , H03M1/0639 , H03M1/1009 , H03M1/1038 , H03M1/124 , H03M1/145 , H03M1/38 , H03M1/462 , H03M1/468
Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.
Abstract translation: 提供了一种使用低功率和小面积的半导体器件，可以实现高精度的校准。 根据实施例的半导体器件包括A / D转换单元和耦合到A / D转换单元的输入侧的保持信号产生电路，并且具有不少于A / D转换单元的两个周期的保持周期， D转换单元。 保持信号生成电路包括：SC积分器，包括耦合到A / D转换单元的输入侧的输入缓冲器，以及耦合到输入缓冲器的输入和输出的反馈电容器; 以及将从A / D转换单元输出的多个比特的输出信号与第一和第二阈值进行比较的逻辑电路，并根据比较结果输出控制SC积分器的极性的控制信号。
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公开(公告)号：US20140203958A1
公开(公告)日：2014-07-24
申请号：US14159511
申请日：2014-01-21
Applicant: Renesas Electronics Corporation
Inventor： Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA , Takashi OSHIMA , Tatsuji MATSUURA
CPC classification number: H03M1/1009 , G11C27/02 , H03F1/02 , H03F1/3211 , H03F3/005 , H03F3/45071 , H03F3/45475 , H03F2203/45171 , H03F2203/45544 , H03H7/004 , H03M1/002 , H03M1/124 , H03M1/38 , H03M1/44
Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.
Abstract translation: 差分信号被无源放大放大，其不是共模电压的参考。 此时，在进行逐次逼近型模拟数字转换操作之前，差分信号的电压被无源放大两次。 无源放大通过提供执行采样操作的多个电容来实现，并且通过使用开关来切换这些连接关系。 在不伴随消耗功率和芯片尺寸的增加的情况下，将比较器的噪声的影响减小到一半，使得有效分辨率可以增加一位。
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公开(公告)号：US20160043729A1
公开(公告)日：2016-02-11
申请号：US14921435
申请日：2015-10-23
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
CPC classification number: H03M1/0607 , H01L23/5225 , H01L23/5226 , H01L23/528 , H01L27/0629 , H01L2924/0002 , H03M1/0604 , H03M1/1023 , H03M1/124 , H03M1/1245 , H03M1/442 , H03M1/46 , H03M1/462 , H03M1/468 , H01L2924/00
Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
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Patent Agency Ranking
公开(公告)号：US20150249459A1
公开(公告)日：2015-09-03
申请号：US14711200
申请日：2015-05-13
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Takashi OSHIMA , Tatsuji MATSUURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA
CPC classification number: H03M1/1033 , H03M1/002 , H03M1/1052 , H03M1/12 , H03M1/201 , H03M1/44 , H03M1/46 , H03M1/66 , H03M1/745
Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.
Abstract translation: 为了补偿包括DA转换单元和AD转换单元的电子系统中的AD转换单元的非线性和DA转换单元的非线性，电子系统包括A / D转换单元，D / A 转换单元，AD转换补偿单元，DA转换补偿单元和校准单元。 在校准操作期间，校准单元设定AD转换补偿单元的工作特性和DA转换补偿单元的工作特性。 在校准操作期间设定的AD转换补偿单元的工作特性补偿A / D转换单元的AD转换的非线性。 在校准操作期间设置的DA转换补偿单元的工作特性补偿D / A转换单元的DA转换的非线性。
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公开(公告)号：US20140333459A1
公开(公告)日：2014-11-13
申请号：US14274813
申请日：2014-05-12
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Takashi OSHIMA , Tatsuji MATSUURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA
CPC classification number: H03M1/1033 , H03M1/002 , H03M1/1052 , H03M1/12 , H03M1/201 , H03M1/44 , H03M1/46 , H03M1/66 , H03M1/745
Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.
Abstract translation: 为了补偿包括DA转换单元和AD转换单元的电子系统中的AD转换单元的非线性和DA转换单元的非线性，电子系统包括A / D转换单元，D / A 转换单元，AD转换补偿单元，DA转换补偿单元和校准单元。 在校准操作期间，校准单元设定AD转换补偿单元的工作特性和DA转换补偿单元的工作特性。 在校准操作期间设定的AD转换补偿单元的工作特性补偿A / D转换单元的AD转换的非线性。 在校准操作期间设置的DA转换补偿单元的工作特性补偿D / A转换单元的DA转换的非线性。
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公开(公告)号：US20130102264A1
公开(公告)日：2013-04-25
申请号：US13657765
申请日：2012-10-22
Applicant: Renesas Electronics Corporation
Inventor： Hideo NAKANE , Keisuke Kimura , Takaya Yamamoto , Tatsuji Matsuura , Ryuichi Ujiie
IPC: G06F3/033
CPC classification number: H03M1/1004 , H03M1/1009 , H04B1/1027
Abstract: Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing.
Abstract translation: 提供了能够在接收操作期间执行背景校准而不会不利地影响接收特性的半导体器件。 在接收操作期间，半导体器件检测在增益改变或接收信道改变时发生无效接收信号的定时，并在检测到的定时执行背景校准。 在这种情况下，由于接收信号无效，进行校准不会进一步降低接收的实质准确性。 此外，只要在随机定时执行背景校准，就不会产生当以固定间隔执行背景校准时将产生的不必要的信号分量。
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公开(公告)号：US20170250697A1
公开(公告)日：2017-08-31
申请号：US15594753
申请日：2017-05-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
CPC classification number: H03M1/0634 , H03M1/002 , H03M1/0617 , H03M1/1009 , H03M1/12 , H03M1/1215 , H03M1/1225
Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
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公开(公告)号：US20160248433A1
公开(公告)日：2016-08-25
申请号：US15142273
申请日：2016-04-29
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
CPC classification number: H03M1/0634 , H03M1/002 , H03M1/0617 , H03M1/1009 , H03M1/12 , H03M1/1215 , H03M1/1225
Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
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