NON-VOLATILE MEMORY DEVICE HAVING SCHOTTKY DIODE

    公开(公告)号:US20240237356A9

    公开(公告)日:2024-07-11

    申请号:US18547502

    申请日:2022-03-21

    Applicant: Peiching LIN

    CPC classification number: H10B61/10 H01L23/528 H10B63/20

    Abstract: A non-volatile memory device includes: an insulation layer; a Schottky diode, which is formed on the insulation layer; a writing wire which is conductive and is electrically connected to a first end of the Schottky diode: a memory unit on the Schottky diode, the memory unit being electrically connected to a second end of the Schottky diode: and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the Schottky diode to write the data into the memory unit.

    Magnetic memory and reading/writing method thereof

    公开(公告)号:US12035539B2

    公开(公告)日:2024-07-09

    申请号:US17480357

    申请日:2021-09-21

    Abstract: The present application provides a magnetic memory and a reading/writing method thereof. The magnetic memory includes at least one cell layer, the cell layer including: a plurality of paralleled first conductors located in a first plane; a plurality of paralleled second conductors located in a second plane, the first plane being parallel to the second plane, a projection of the second conductor on the first plane intersecting with the first conductor; a plurality of memory elements arranged between the first plane and the second plane, the memory element including a magnetic tunnel junction and a bidirectional gating device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction being connected to the first conductor, the bidirectional gating device being connected to the second conductor, and the bidirectional gating device being configured to be turned on when a threshold voltage and/or a threshold current are/is applied.

    MEMORY DEVICE
    43.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号:US20240215259A1

    公开(公告)日:2024-06-27

    申请号:US18478213

    申请日:2023-09-29

    CPC classification number: H10B61/10

    Abstract: A memory device of embodiments includes a memory cell including: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a variable resistance layer provided between the third conductive layer and the second conductive layer. The switching layer contains antimony (Sb), a second element, and an oxide of a first element. The first element is at least one element selected from a group consisting of zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), and titanium (Ti). The second element is at least one element selected from a group consisting of carbon (C), boron (B), nitrogen (N), silicon (Si), and tin (Sn).

    Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning

    公开(公告)号:US12004357B2

    公开(公告)日:2024-06-04

    申请号:US17654768

    申请日:2022-03-14

    CPC classification number: H10B61/10 H10N50/01 H10N50/80

    Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.

    Magnetic memory device
    46.
    发明授权

    公开(公告)号:US11980104B2

    公开(公告)日:2024-05-07

    申请号:US17117813

    申请日:2020-12-10

    CPC classification number: H10N50/80 H10B61/10 H10N50/85

    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a variable magnetization direction, a third magnetic layer having a fixed magnetization direction and a nonmagnetic layer, the first magnetic layer being provided between the second and third magnetic layers, and the nonmagnetic layer being provided between the first and third magnetic layers. The second magnetic layer has a superlattice structure in which first element layers and second element layers are alternately stacked. The first element is Co, and the second element is selected from Pt, Ni and Pd, and the second magnetic layer contains Cr as a third element.

    MAGNETIC MEMORY DEVICE
    49.
    发明公开

    公开(公告)号:US20240099021A1

    公开(公告)日:2024-03-21

    申请号:US18465759

    申请日:2023-09-12

    CPC classification number: H10B61/10

    Abstract: According to one embodiment, a magnetic memory device includes a lower insulating layer, first and second conductive portions provided in the lower insulating layer, first and second memory cells provided on the lower insulating layer and on the respective first and second conductive portions, and each including a magnetoresistance effect element, a switching element and a bottom electrode connected to corresponding one of the first and second conductive portions. As viewed from a third direction, a width of each of the first and second conductive portions is less than a width of a corresponding bottom electrode. The lower insulating layer has a void under a region between the first and second memory cells.

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