-
公开(公告)号:US20240237356A9
公开(公告)日:2024-07-11
申请号:US18547502
申请日:2022-03-21
Applicant: Peiching LIN
Inventor: Peiching LING , Nanray WU
IPC: H10B61/00 , H01L23/528 , H10B63/00
CPC classification number: H10B61/10 , H01L23/528 , H10B63/20
Abstract: A non-volatile memory device includes: an insulation layer; a Schottky diode, which is formed on the insulation layer; a writing wire which is conductive and is electrically connected to a first end of the Schottky diode: a memory unit on the Schottky diode, the memory unit being electrically connected to a second end of the Schottky diode: and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the Schottky diode to write the data into the memory unit.
-
公开(公告)号:US12035539B2
公开(公告)日:2024-07-09
申请号:US17480357
申请日:2021-09-21
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor: Baolei Wu , Xiaoguang Wang , Yulei Wu
CPC classification number: H10B61/10 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H10B61/22 , H10N50/80
Abstract: The present application provides a magnetic memory and a reading/writing method thereof. The magnetic memory includes at least one cell layer, the cell layer including: a plurality of paralleled first conductors located in a first plane; a plurality of paralleled second conductors located in a second plane, the first plane being parallel to the second plane, a projection of the second conductor on the first plane intersecting with the first conductor; a plurality of memory elements arranged between the first plane and the second plane, the memory element including a magnetic tunnel junction and a bidirectional gating device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction being connected to the first conductor, the bidirectional gating device being connected to the second conductor, and the bidirectional gating device being configured to be turned on when a threshold voltage and/or a threshold current are/is applied.
-
公开(公告)号:US20240215259A1
公开(公告)日:2024-06-27
申请号:US18478213
申请日:2023-09-29
Applicant: Kioxia Corporation
Inventor: Yuya SATO , Masakazu GOTO , Hiroki KAWAI , Takeshi IWASAKI , Katsuyoshi KOMATSU
IPC: H10B61/00
CPC classification number: H10B61/10
Abstract: A memory device of embodiments includes a memory cell including: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a variable resistance layer provided between the third conductive layer and the second conductive layer. The switching layer contains antimony (Sb), a second element, and an oxide of a first element. The first element is at least one element selected from a group consisting of zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), and titanium (Ti). The second element is at least one element selected from a group consisting of carbon (C), boron (B), nitrogen (N), silicon (Si), and tin (Sn).
-
公开(公告)号:US12020737B2
公开(公告)日:2024-06-25
申请号:US17464808
申请日:2021-09-02
Applicant: Kioxia Corporation
Inventor: Hisanori Aikawa
CPC classification number: G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , H10B61/10 , H10N50/01 , H10N50/10 , H10N50/85
Abstract: A memory device includes a memory cell array, first and second memory cells, first and second read circuits, and first and second write circuits. The memory cell array includes first and second sub-arrays. The first memory cells are included in each of the first sub-arrays. The second memory cells are included in each of the second sub-arrays. The first and second read circuits are provided for reading data of the first and second memory cells, respectively. The first and second write circuits are provided for writing data to the first and second memory cells, respectively. An area of the first sub-array is different from an area of the second sub-array.
-
45.
公开(公告)号:US12004357B2
公开(公告)日:2024-06-04
申请号:US17654768
申请日:2022-03-14
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Lei Wan , Jordan Katine , Tsai-Wei Wu , Chu-Chen Fu
Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.
-
公开(公告)号:US11980104B2
公开(公告)日:2024-05-07
申请号:US17117813
申请日:2020-12-10
Applicant: Kioxia Corporation
Inventor: Masaru Toko , Hideyuki Sugiyama , Soichi Oikawa , Masahiko Nakayama
Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a variable magnetization direction, a third magnetic layer having a fixed magnetization direction and a nonmagnetic layer, the first magnetic layer being provided between the second and third magnetic layers, and the nonmagnetic layer being provided between the first and third magnetic layers. The second magnetic layer has a superlattice structure in which first element layers and second element layers are alternately stacked. The first element is Co, and the second element is selected from Pt, Ni and Pd, and the second magnetic layer contains Cr as a third element.
-
公开(公告)号:US20240130140A1
公开(公告)日:2024-04-18
申请号:US18395762
申请日:2023-12-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ting-Hsiang Huang , Yi-Chung Sheng , Sheng-Yuan Hsueh , Kuo-Hsing Lee , Chih-Kai Kang
Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.
-
公开(公告)号:US11942466B2
公开(公告)日:2024-03-26
申请号:US17839431
申请日:2022-06-13
Applicant: Kioxia Corporation
Inventor: Mutsumi Okajima
CPC classification number: H01L25/50 , H01L24/08 , H01L24/80 , H01L25/18 , G11C11/161 , G11C11/407 , H01L21/02244 , H01L21/02258 , H01L2224/08145 , H01L2224/8013 , H01L2924/1436 , H10B12/033 , H10B61/10
Abstract: According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.
-
公开(公告)号:US20240099021A1
公开(公告)日:2024-03-21
申请号:US18465759
申请日:2023-09-12
Applicant: Kioxia Corporation
Inventor: Naoki AKIYAMA , Kenichi YOSHINO , Kazuya SAWADA , Hyungjun CHO , Takuya SHIMANO
IPC: H10B61/00
CPC classification number: H10B61/10
Abstract: According to one embodiment, a magnetic memory device includes a lower insulating layer, first and second conductive portions provided in the lower insulating layer, first and second memory cells provided on the lower insulating layer and on the respective first and second conductive portions, and each including a magnetoresistance effect element, a switching element and a bottom electrode connected to corresponding one of the first and second conductive portions. As viewed from a third direction, a width of each of the first and second conductive portions is less than a width of a corresponding bottom electrode. The lower insulating layer has a void under a region between the first and second memory cells.
-
公开(公告)号:US11910621B2
公开(公告)日:2024-02-20
申请号:US16283455
申请日:2019-02-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jau-Yi Wu
CPC classification number: H10B63/24 , H10B61/10 , H10N50/01 , H10N70/063 , H10N70/066 , H10N70/231 , H10N70/24 , H10N70/826 , H10N70/841 , H01F10/3254 , H10N50/80 , H10N50/85 , H10N70/8825 , H10N70/8828 , H10N70/8833
Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate. A bottom electrode via opening is formed in the dielectric layer. A bottom electrode is formed in the bottom electrode via opening. The bottom electrode is etched back. A selector is formed in the bottom electrode via opening and over the bottom electrode. A memory layer is formed over the selector. A top electrode is formed over the memory layer.
-
-
-
-
-
-
-
-
-