公开(公告)号：US6150058A

公开(公告)日：2000-11-21

申请号：US97144

申请日：1998-06-12

Applicant: Chih-Chiang Tu ,  San-De Tzu

Inventor： Chih-Chiang Tu ,  San-De Tzu

IPC: G03F1/00 ,  G03F1/32 ,  G03F1/78 ,  G03F7/20 ,  G03F9/00

CPC classification number: G03F7/2063 ,  G03F1/32 ,  G03F1/78

Abstract: A mask and method of forming a mask for forming electrode patterns having both closely spaced lines and lines with greater separation between them. The mask uses a pattern formed using attenuating phase shifting material for the region of the mask with lines with greater separation and a binary pattern formed using opaque material in the region of the mask with closely spaced lines. The mask design data is used to determine the mask regions using attenuating phase shifting material and the regions of the mask using a binary pattern. The mask is illuminated using off axis illumination, preferably quadrapole off axis illumination. The mask is formed using electron beam exposure of a resist using more than one exposure dose so that only one layer of resist is required to form the two regions of the mask one using attenuating phase shifting material and one using a binary pattern.

Abstract translation: 形成掩模的掩模和方法，用于形成具有彼此间隔很远的线和线的电极图案，并且它们之间具有更大的间隔。 掩模使用通过使用衰减相移材料形成的图案，用于具有较大分离的线的掩模区域，并且使用不透明材料在具有紧密间隔的线的区域中形成二元图案。 掩模设计数据用于使用衰减相移材料和掩模的区域使用二进制图案来确定掩模区域。 使用离轴照明照亮掩模，最好是四极偏离轴照明。 使用多于一个曝光剂量的抗蚀剂的电子束曝光来形成掩模，使得仅使用一层抗蚀剂来形成使用衰减相移材料的掩模一个的两个区域，而使用二元图案形成掩模的两个区域。

公开(公告)号：US5266424A

公开(公告)日：1993-11-30

申请号：US849602

申请日：1992-03-12

Applicant: Takeshi Fujino ,  Yaichiro Watakabe

Inventor： Takeshi Fujino ,  Yaichiro Watakabe

IPC: G03F1/76 ,  G03F1/78 ,  G03F7/004 ,  G03F7/039 ,  G03F7/26 ,  G03F7/36 ,  G03F7/38 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

CPC classification number: G03F7/36 ,  G03F7/039 ,  G03F7/265

Abstract: The present invention is mainly directed to provision of a method of producing a highly precise resist pattern, even when a high energy beam is used. Resist containing a base resin including a hydroxyl group, an acid generating agent irradiated with radiation for generating sulfonic acid, and a cross linking agent reacting with the hydroxyl group of the base resin by the catalytic action of the proton of the sulfonic acid thereby cross linking said base resin is applied onto a substrate. The resist is irradiated selectively with radiation, whereby the resist is divided into the exposed part and the non exposed part and the sulfonic acid is generated in the resist of the exposed part. The resist is heated to a first temperature so as to cross link the irradiated part of the resist. The resist is heated to a second temperature and exposed in an atmosphere of a silylating agent, and the surface of the exposed part of the resist is silylated. The resist is dry-developed with oxygen plasma.

Abstract translation: 本发明主要涉及提供一种制造高精度抗蚀剂图案的方法，即使使用高能量束也是如此。 含有羟基的基础树脂，用辐射产生磺酸的酸产生剂的抗蚀剂和通过磺酸的质子的催化作用与基础树脂的羟基反应的交联剂进行交联 所述基础树脂施加到基底上。 用辐射选择性地照射抗蚀剂，由此将抗蚀剂分成暴露部分和非暴露部分，并且在暴露部分的抗蚀剂中产生磺酸。 将抗蚀剂加热至第一温度，以使抗蚀剂的照射部分交联。 将抗蚀剂加热至第二温度并在甲硅烷基化剂的气氛中暴露，并将抗蚀剂的暴露部分的表面甲硅烷基化。 抗氧化剂用氧等离子体干发展。

公开(公告)号：US20240353751A1

公开(公告)日：2024-10-24

申请号：US18305978

申请日：2023-04-24

Applicant: TEL Manufacturing and Engineering of America, Inc.

Inventor： Angelique Raley ,  Luis Fernandez ,  Brian Pfeifer ,  Joshua Larose

IPC: G03F1/78 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20

CPC classification number: G03F1/78 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20

Abstract: A method for processing a substrate with a gas cluster ion beam (GCIB) that includes: receiving, at a GCIB controller, control signals from a tool controller to change a GCIB process parameter during a GCIB scanning process, the changing in the GCIB process parameter associated with a variation in the depth of recesses to be formed over the substrate with the GCIB scanning process; and performing the GCIB scanning process in a GCIB process chamber, the performing including scanning a GCIB across a portion of the substrate according to the control signals to form the recesses with varying depths, the variation in the depth of the recesses having a gradient associated with the change in the GCIB process parameter.

公开(公告)号：US20240210815A1

公开(公告)日：2024-06-27

申请号：US18601592

申请日：2024-03-11

Applicant: D2S, Inc.

Inventor： Akira Fujimura ,  P. Jeffrey Ungar ,  Nagesh Shirali

IPC: G03F1/36 ,  G03F1/78

CPC classification number: G03F1/36 ,  G03F1/78

Abstract: Methods and systems for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The methods and systems also include calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.

公开(公告)号：US11940737B2

公开(公告)日：2024-03-26

申请号：US17315087

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsueh-Yi Chung ,  Yung-Cheng Chen ,  Fei-Gwo Tsai ,  Chi-Hung Liao ,  Shih-Chi Fu ,  Wei-Ti Hsu ,  Jui-Ping Chuang ,  Tzong-Sheng Chang ,  Kuei-Shun Chen ,  Meng-Wei Chen

IPC: G03F7/20 ,  G03F1/50 ,  G03F1/68 ,  G03F1/70 ,  G03F1/78 ,  G03F7/00 ,  H01L21/66

CPC classification number: G03F7/70433 ,  G03F1/50 ,  G03F1/68 ,  G03F1/70 ,  G03F1/78 ,  G03F7/20 ,  G03F7/70141 ,  G03F7/70158 ,  G03F7/70716 ,  H01L22/30

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

公开(公告)号：US11934096B2

公开(公告)日：2024-03-19

申请号：US17288321

申请日：2019-10-23

Applicant: KYOCERA Corporation

Inventor： Shigenobu Furukawa ,  Koji Akashi

IPC: G03F1/78 ,  G03F7/20 ,  H01J37/305

CPC classification number: G03F1/78 ,  G03F7/2002 ,  H01J37/305

Abstract: A frame member for an electron beam lithography device of the present disclosure includes a frame body comprising sapphire or aluminum oxide-based ceramics having an open porosity of 0.2% or less and a conductive film disposed at least on a main surface of an electron gun side of the frame body.

公开(公告)号：US20230095091A1

公开(公告)日：2023-03-30

申请号：US18057471

申请日：2022-11-21

Applicant: NuFlare Technology, Inc.

Inventor： Yasuo KATO ,  Ryoh KAWANA

IPC: H01J37/304 ,  H01J37/317 ,  G03F7/20 ,  G03F1/78

Abstract: A multi-charged particle beam writing apparatus includes a circuit to allocate an additional dose to a position inside a writing target pattern in order to change a first dose distribution by an excessive dose, generated on the target object by applying, in the multi-charged particle beams, an excessive dose defective beam, to a second dose distribution whose center is located inside the writing target pattern and for which beam irradiation canceling out the excessive dose and being in a range of the first dose distribution exists; and a circuit to perform correction by subtracting an increased dose amount, generated at the center of the second dose distribution because of the additional dose being allocated, from a dose with which one of the center of the second dose distribution and a vicinity of the center of the second dose distribution is irradiated.

公开(公告)号：US20230074316A1

公开(公告)日：2023-03-09

申请号：US17826796

申请日：2022-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soeun Shin ,  Minah Kim ,  Jin Choi

IPC: G03F1/36 ,  G03F1/86 ,  G03F1/78 ,  G03F1/70 ,  G03F7/20

Abstract: Methods of fabricating lithographic masks include performing mask process correction (MPC) on a mask tape out (MTO) design layout. Performing MPC may include identifying a plurality of unit cells (each being iterated in the MTO design layout and including a plurality of curve patterns), and performing model-based MPC on at least one of the plurality of unit cells. These methods may further include performing electron beam exposure based on the MTO design layout on which the MPC is performed. The performing model-based MPC on at least one of the plurality of unit cells may be based on at least one of an aspect ratio, sizes, curvatures of curved edges, density, and a duty of the plurality of curve patterns.

公开(公告)号：US20230034170A1

公开(公告)日：2023-02-02

申请号：US17444142

申请日：2021-07-30

Applicant: D2S, Inc.

Inventor： Akira Fujimura ,  P. Jeffrey Ungar ,  Nagesh Shirali

IPC: G03F1/78 ,  G03F1/36 ,  G06F30/20 ,  G06F30/392

Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

公开(公告)号：US11526081B2

公开(公告)日：2022-12-13

申请号：US17366319

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.