公开(公告)号：US3971998A

公开(公告)日：1976-07-27

申请号：US574028

申请日：1975-05-02

Applicant: Bhaskarpillai Gopinath ,  Robert Paul Kurshan

Inventor： Bhaskarpillai Gopinath ,  Robert Paul Kurshan

IPC: H03B5/00 ,  H03B28/00 ,  H03D1/00 ,  H03D3/00 ,  H03H15/00 ,  H03H15/02 ,  H03H17/00 ,  H03H17/04 ,  H03H21/00 ,  H04B1/06 ,  H04B3/04 ,  H04L27/00 ,  H04W84/00 ,  H04B15/00 ,  H03B1/04

CPC classification number: H04W84/00 ,  H03B28/00 ,  H03D1/00 ,  H03D3/00 ,  H03H17/028 ,  H03H17/04 ,  H04B1/06

Abstract: Disclosed is a recursive circuit capable of serving as a signal detector or as a signal generator. The circuit comprises a shift register capable of storing multilevel signals, and a feedback network responsive to an input signal and to the output signals of selected stages of the shift register. In the feedback network, the output signals of the selected stages are each multiplied by prechosen integers, and then added with the input signal to form a sum signal which is applied to the first stage of the shift register. The sum signal is developed by nonmodulo addition, and the multiplying integers are prechosen to cause the characteristic function of the circuit to be a cyclotomic polynomial. Detection of the presence in the input signal of a signal having a chosen frequency is accomplished by the sum signal excluding a predetermined threshold level. Signal generation is accomplished by presetting the register to a nonzero state and allowing the output signal to develop in accordance with the characteristic function of the circuit.

Abstract translation: 公开了能够用作信号检测器或信号发生器的递归电路。 该电路包括能够存储多电平信号的移位寄存器和响应于输入信号和移位寄存器的选定级的输出信号的反馈网络。 在反馈网络中，所选级的输出信号各乘以预选整数，然后与输入信号相加，形成加到移位寄存器的第一级的和信号。 总和信号是通过非模态加法产生的，并且乘法整数被预先选择以使电路的特征函数成为一个循环多项式。 通过除了预定阈值电平之和的和信号来检测在具有选定频率的信号的输入信号中的存在。 通过将寄存器预置到非零状态并根据电路的特征功能允许输出信号产生来实现信号生成。

公开(公告)号：US3935477A

公开(公告)日：1976-01-27

申请号：US512848

申请日：1974-10-07

Applicant: Robert Joseph Strain ,  Robert Henry Walden

Inventor： Robert Joseph Strain ,  Robert Henry Walden

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768 ,  H03F3/16 ,  H03H15/02 ,  H03K19/40 ,  H01L27/04 ,  H01L29/80

CPC classification number: G11C27/04 ,  H01L29/76875 ,  H03F3/16 ,  H03H15/02

Abstract: In charge transfer apparatus, an analog inverter comprises a charge storage medium to which are applied varying voltages through a plurality of electrodes, illustratively: a source electrode, a reference electrode and a collector electrode arranged in tandem. Between the source and reference electrodes there is a first control electrode and, in one embodiment, between the reference and collector electrodes there is a second control electrode and a signal electrode. With the electrical signal to be inverted connected to the signal electrode, analog inversion, a form of complementing function, occurs as follows: (1) during the first phase of the clock cycle, a voltage is applied to the first control electrode effective to cause a fixed amount of charge to be transferred from the source to a reference potential well established under the reference electrode; (2) during the second phase of the clock cycle, a voltage is applied to the second control electrode effective to increase the surface potential thereunder and to permit charge to be transferred into a potential well under the collector electrode; this charge establishes a new surface potential which, apart from an additive constant is equal to the inverted signal voltage. In other embodiments in which the analog signal is of a self-strobing type (e.g., the output of a C4D or BB) the second control electrode is not required.

Abstract translation: 在电荷转移装置中，模拟反相器包括电荷存储介质，电荷存储介质通过多个电极施加变化的电压，例如：串联布置的源电极，参考电极和集电极。 在源极和参考电极之间存在第一控制电极，并且在一个实施例中，在参考电极和集电极之间存在第二控制电极和信号电极。 在电信号被反相连接到信号电极的情况下，模拟反相（一种形式的互补功能）发生如下：（1）在时钟周期的第一阶段期间，向第一控制电极施加电压以有效地引起 将固定量的电荷从源极转移到参考电极下良好建立的参考电位; （2）在时钟周期的第二阶段期间，向第二控制电极施加电压，有效地增加其周围的表面电位，并允许电荷转移到集电极下方的势阱中; 该电荷建立新的表面电位，除了加法常数等于反相信号电压之外。 在其中模拟信号具有自选频型（例如，C4D或BB的输出）的其它实施例中，不需要第二控制电极。

公开(公告)号：US3935439A

公开(公告)日：1976-01-27

申请号：US487105

申请日：1974-07-12

Applicant: Dennis Darcy Buss ,  Walter Howard Bailey

Inventor： Dennis Darcy Buss ,  Walter Howard Bailey

IPC: G06G7/19 ,  H03H15/02 ,  G11C11/40

CPC classification number: G06G7/1907 ,  H03H15/02 ,  H03H2015/026

Abstract: A variable tap weight convolution filter comprised of charge transfer devices which may be charge coupled devices, bucket brigade devices or a combination of the two, for performing convolutions of an input signal with tap weights from a second input signal, said tap weights varying as a function of time.

Abstract translation: 一种可变抽头权重卷积滤波器，其包括可以是电荷耦合器件，桶式装置或两者的组合的电荷转移装置，用于执行输入信号与来自第二输入信号的抽头权重的卷积，所述抽头权重变化为 时间的功能

公开(公告)号：US3931510A

公开(公告)日：1976-01-06

申请号：US487104

申请日：1974-07-12

Applicant: Allan R. Kmetz

Inventor： Allan R. Kmetz

IPC: G11C27/04 ,  H03H15/02 ,  G11C11/40 ,  H03K5/159

CPC classification number: H03H15/02 ,  G11C27/04

Abstract: A dispersion compensated CTD controlled data display where a serial-parallel-serial CTD is loaded at a low data rate with clock means to shift data from the CTD at a high data rate. A transversal filter is connected in series with the CTD to provide a dispersion corrected output of the data. The output is applied to the input of the CTD at the high data rate and to a display unit with reloading of the CTD to change the display.

Abstract translation: 色散补偿CTD控制数据显示，其中串行并行串行CTD以低数据速率加载，具有时钟装置，以高数据速率从CTD移位数据。 横向滤波器与CTD串联连接以提供数据的色散校正输出。 输出以高数据速率应用于CTD的输入，并且通过重新加载CTD来更改显示器。

公开(公告)号：US3621402A

公开(公告)日：1971-11-16

申请号：US3621402D

申请日：1970-08-03

Applicant: BELL TELEPHONE LABOR INC

Inventor： GARDNER WILLIAM ALLEN

IPC: H03H15/02 ,  H03K23/00

CPC classification number: H03H15/02

Abstract: A sampled data filter is disclosed comprising a plurality of amplifiers interconnected by delay units and feedback resistors. Each delay unit comprises the cascade connection of actuable switches and storage capacitors. The values of the capacitors and feedback resistors are preselected to obtain a desired transfer function and to nullify the effects of residual capacitor charge.

公开(公告)号：US20220006446A1

公开(公告)日：2022-01-06

申请号：US17280105

申请日：2019-09-24

Applicant: UNIVERSITEIT GENT ,  IMEC VZW

Inventor： Guy TORFS ,  Michiel VERPLAETSE

IPC: H03H17/02 ,  H03H15/02 ,  H03H17/06

Abstract: A filter includes cascaded building blocks, for filtering an incoming signal. Each building block has first and second delay elements. A first scaling device is between an input node of the first delay element and an output node of the second delay element, and a second scaling device is between an output node of the first delay element and an input node of the second delay element. The building block has a cross scaling device between the output nodes of the first delay element and of the second delay element, and/or between the input nodes of the first delay element and of the second delay element. The building block is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.

公开(公告)号：US10313165B2

公开(公告)日：2019-06-04

申请号：US15453774

申请日：2017-03-08

Applicant: Credo Technology Group Limited

Inventor： Lawrence Chi Fung Cheng ,  Haihui Luo

IPC: H03F3/21 ,  H03F3/193 ,  H04L25/03 ,  H04L27/01 ,  H03F3/45 ,  H03G5/28 ,  H03H11/26 ,  H03H15/02

Abstract: High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

公开(公告)号：US10056881B2

公开(公告)日：2018-08-21

申请号：US15443443

申请日：2017-02-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Iman Madadi ,  Massoud Tohidian ,  Robert Bogdan Staszewski

IPC: H03H15/02 ,  H03H19/00 ,  H03H15/00

CPC classification number: H03H19/004 ,  H03H15/00 ,  H03H15/023

Abstract: A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.

公开(公告)号：US09940415B2

公开(公告)日：2018-04-10

申请号：US15019445

申请日：2016-02-09

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson ,  Hu Jing Yao ,  Dustin Forman

IPC: G06F17/50 ,  H03H15/02 ,  H03K5/15 ,  H03K5/1536

CPC classification number: G06F17/5009 ,  H03H15/02 ,  H03K5/15 ,  H03K5/1536

Abstract: A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.

公开(公告)号：US09698759B2

公开(公告)日：2017-07-04

申请号：US14269647

申请日：2014-05-05

Applicant: ANALOG DEVICES, INC.

Inventor： Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

IPC: H01B1/10 ,  H03H15/02 ,  G01R27/26 ,  G06G7/19 ,  G06F17/14 ,  G01D5/24 ,  G01R31/02

CPC classification number: H03H15/02 ,  G01D5/24 ,  G01R27/2605 ,  G01R31/028 ,  G06F17/14 ,  G06G7/19

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.