公开(公告)号：US5400290A

公开(公告)日：1995-03-21

申请号：US141002

申请日：1993-10-26

申请人： Katsuhiro Suma ,  Masaki Tsukude ,  Yukinobu Adachi

发明人： Katsuhiro Suma ,  Masaki Tsukude ,  Yukinobu Adachi

IPC分类号： G01R31/28 ,  G01R19/165 ,  G01R31/3185 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/46 ,  G11C29/50 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C8/00

CPC分类号： G11C29/028 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401 ,  G11C2029/5004

摘要： In response to an external control signal, a first timing detecting circuit and a high voltage detecting circuit detect setting of a signature mode and provide a signature mode signal to a second timing detecting circuit. The second timing detecting circuit outputs an output buffer activating signal to the output buffer in response to the external control signal. In response to the output buffer activating signal, the output buffer detects an internal supply voltage and provides the same to an external pin.

摘要翻译： 响应于外部控制信号，第一定时检测电路和高电压检测电路检测签名模式的设置，并向第二定时检测电路提供签名模式信号。 第二定时检测电路响应外部控制信号向输出缓冲器输出输出缓冲器激活信号。 响应于输出缓冲器激活信号，输出缓冲器检测内部电源电压并将其提供给外部引脚。

公开(公告)号：US5396465A

公开(公告)日：1995-03-07

申请号：US156779

申请日：1993-11-24

申请人： Seung-Cheol Oh ,  Yong-Sik Seok

发明人： Seung-Cheol Oh ,  Yong-Sik Seok

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C29/50 ,  G11C11/401

摘要： A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.

摘要翻译： 半导体存储器件具有设置在公共位读出放大器和存储器阵列之间的相邻存储器阵列和隔离晶体管。 根据本发明的隔离控制电路在老化操作模式期间产生电源电压Vcc（而不是升压电压Vpp），从而防止隔离晶体管的栅极氧化层被破坏或劣化。

公开(公告)号：US5363333A

公开(公告)日：1994-11-08

申请号：US129375

申请日：1993-09-30

申请人： Akira Tsujimoto

发明人： Akira Tsujimoto

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  G11C13/00

CPC分类号： G11C29/50 ,  G11C11/401

摘要： A power supply system incorporated in a dynamic random access memory device distributes a step-down power voltage and a boosted voltage to a sense amplifier unit and a word line driver for allowing switching transistors of the memory cells to transfer the step-down voltage level to the storage capacitor without any voltage drop in read-out and write-in modes, and the switching transistors and the storage capacitors are subjected to inspections through a burn-in testing process before delivery from the manufacturing factory so as to actualize potential failure; however, either switching transistors or storage capacitors are insufficiently stressed in the burn-in testing process, and the power supply system changes the ratio of the boosted voltage to the step-down power voltage between the read-out and write-in modes and the burn-in testing process so that the switching transistors and the storage capacitors are sufficiently stressed.

摘要翻译： 结合在动态随机存取存储器件中的电源系统将降压电源电压和升压电压分配给读出放大器单元和字线驱动器，以允许存储单元的开关晶体管将降压电压传递到 在读出和写入模式中没有任何电压降的存储电容器，并且开关晶体管和存储电容器在从制造工厂交付之前通过老化测试过程进行检查，以实现潜在的故障; 然而，在老化测试过程中，开关晶体管或存储电容器的应力不足，并且电源系统改变升压电压与读出和写入模式之间的降压功率电压的比率 老化测试过程，使得开关晶体管和存储电容器受到足够的应力。

公开(公告)号：US5287312A

公开(公告)日：1994-02-15

申请号：US813492

申请日：1991-12-26

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4087 ,  G11C29/50 ,  G11C8/12 ,  G11C11/401

摘要： A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.

摘要翻译： 根据本发明的动态随机存取存储器包括以行和列排列的多个动态存储器单元，连接到同一行上的存储器单元的字线，连接到同一列上的存储器单元的位线， 字线选择电路，具有响应于内部地址信号选择任意一行的字线选择功能，字线驱动电压源，字线驱动电路，具有连接在字线之间的至少一个驱动MOS晶体管 驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号来控制字线驱动 使得字线驱动电路在接收到外部地址信号时比在正常操作模式中选择的字线更多地驱动字线。

公开(公告)号：US5276647A

公开(公告)日：1994-01-04

申请号：US813438

申请日：1991-12-26

申请人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

发明人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

IPC分类号： G11C11/413 ,  G01R31/28 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C8/12 ,  G11C11/41

摘要： SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

摘要翻译： SRAM包括字线驱动电路，其根据正常操作时的输入地址选择预定数量的字线，并且同时选择大于所选择的字线数量的所有字线或字线 在正常工作时，在电压应力测试时，以及在正常工作时向所述一对位线施加预定偏置电压的位线负载电路，并且将偏置电压控制为不 施加到所述一对位线中的至少一个或在电压应力测试时施加低于正常操作时的偏置电压的偏置电压。

公开(公告)号：US5208777A

公开(公告)日：1993-05-04

申请号：US801375

申请日：1991-12-02

申请人： Kazuo Shibata

发明人： Kazuo Shibata

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50

CPC分类号： G11C29/50 ,  G11C11/401

摘要： A circuit for carrying out ordinary "write" and "read" operation during operation of applying a test voltage to a cell opposite electrode in test operation is provided. The circuit converts a test mode instruction signal to an ordinary operation instruction signal in a semiconductor memory device. The test mode instruction signal can be applied to an input pin of the semiconductor memory device, so that the test operation can be carried out even after the assembly of the semiconductor memory device.

公开(公告)号：US5111136A

公开(公告)日：1992-05-05

申请号：US746148

申请日：1991-08-14

申请人： Hiromi Kawashima

发明人： Hiromi Kawashima

IPC分类号： G01R19/165 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G06F15/78 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  H03K19/00

CPC分类号： G01R31/31701

摘要： A test mode input detection circuit for a semiconductor device comprises a first circuit including a group of transistors and a load element, the transistors and load element being connected in series between a power source and an input terminal, a node between the transistor group and the load element forming an output terminal of the first circuit; a second circuit including a transistor whose gate receives an output from the output terminal of the first circuit, and a transistor whose gate receives a power source voltage, these transistors being connected in series between the power source and a ground, a node between the transistors forming an output terminal of the second circuit; and an inverter circuit for providing a test mode signal in response to an output of the second circuit.

摘要翻译： 一种用于半导体器件的测试模式输入检测电路包括：第一电路，包括一组晶体管和负载元件，晶体管和负载元件串联连接在电源和输入端之间，晶体管组与 负载元件形成第一电路的输出端子; 第二电路，其包括栅极接收来自第一电路的输出端的输出的晶体管，以及栅极接收电源电压的晶体管，这些晶体管串联连接在电源和地之间，晶体管之间的节点 形成所述第二电路的输出端子; 以及用于响应于第二电路的输出提供测试模式信号的逆变器电路。

公开(公告)号：US4956816A

公开(公告)日：1990-09-11

申请号：US358482

申请日：1989-05-30

申请人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobuaki Otsuka

发明人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobuaki Otsuka

IPC分类号： G11C17/00 ,  G11C16/34 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50

CPC分类号： G11C29/50004 ,  G11C16/34 ,  G11C29/50 ,  G11C29/50016 ,  G06F2201/81 ,  G11C16/04

摘要： This invention provides a non-volatile semiconductor memory having a first node and a second node, the second node having a ground potential. The invention includes a plurality of non-volatile memory cells each having a drain and a threshold potential, the cells, for storing data written into the cells at a predetermined normal writing voltage. A plurality of bit lines, each memory cell being connected to one of the bit lines, transfer data to and from the memory cells. A circuit connected to the bit lines simultaneously tests the memory cells of all the bit lines at the normal writing voltage to detect changes in the threshold potential.

摘要翻译： 本发明提供一种具有第一节点和第二节点的非易失性半导体存储器，第二节点具有接地电位。 本发明包括多个具有漏极和阈值电位的非易失性存储单元，用于存储以预定的正常写入电压写入单元的数据。 多个位线，每个存储单元连接到一个位线，将数据传送到存储单元和从存储单元传送数据。 连接到位线的电路同时以正常写入电压测试所有位线的存储单元，以检测阈值电位的变化。

公开(公告)号：US4821238A

公开(公告)日：1989-04-11

申请号：US895091

申请日：1986-08-11

申请人： Takeo Tatematsu

发明人： Takeo Tatematsu

IPC分类号： G11C29/00 ,  G11C11/34 ,  G11C29/06 ,  G11C29/36 ,  G11C7/00

CPC分类号： G11C29/36

摘要： A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit; an element for receiving external signals supplied from the outside; and an input switching circuit connected between the test pattern generating circuit and the receiving element, for switching the input supplied to the internal circuit between output signals generating from the test pattern generating circuit and the external signals, the output signals generated from the test pattern generated circuit being input to the internal circuit through the input switching circuit in a test mode, the external signals being input to the internal circuit through the input switching circuit in a usual mode; the test pattern generating circuit, the input switching circuit, and the internal circuit being provided on the same chip.

摘要翻译： 半导体存储器件包括内部电路，其包括存储器电路; 测试图形发生电路; 用于接收从外部提供的外部信号的元件; 连接在测试图形发生电路和接收元件之间的输入开关电路，用于切换从测试图形发生电路产生的输出信号和外部信号之间提供给内部电路的输入，从产生的测试图形产生的输出信号 电路在测试模式下通过输入开关电路输入到内部电路，外部信号通过输入开关电路以通常模式输入到内部电路; 测试图形发生电路，输入开关电路和内部电路设置在同一芯片上。

公开(公告)号：US4802137A

公开(公告)日：1989-01-31

申请号：US7582

申请日：1987-01-28

申请人： Taizo Okuda ,  Shinji Saito ,  Nobuo Shishikura

发明人： Taizo Okuda ,  Shinji Saito ,  Nobuo Shishikura

IPC分类号： G11C29/00 ,  G11C16/04 ,  G11C17/00 ,  G11C29/06 ,  G11C29/24 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/24 ,  G11C29/50 ,  G11C16/04

摘要： A semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each coupled to the memory cells forming one column, and a MOS transistor connected between a power supply terminal and one end of every bit line. The device further includes at least one test memory cell coupled in series with the MOS transistor, thus forming a series circuit connected between the power supply terminal and the ground.

摘要翻译： 半导体存储器件包括排列成行和列的多个存储器单元，多个位线，每个位线连接到形成一列的存储器单元，以及连接在电源端子和每个位线的一端之间的MOS晶体管。 该装置还包括与MOS晶体管串联耦合的至少一个测试存储单元，从而形成连接在电源端子和地之间的串联电路。