公开(公告)号：US10122552B2

公开(公告)日：2018-11-06

申请号：US14853520

申请日：2015-09-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland van der Tuijn

IPC: H04L7/06 ,  H04L25/02 ,  H04B10/079 ,  G06F13/40

Abstract: A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.

公开(公告)号：US10108530B2

公开(公告)日：2018-10-23

申请号：US15270323

申请日：2016-09-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Lydie Terras ,  William Orlando

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/38 ,  G06F21/64 ,  G06F9/00 ,  G06F21/52 ,  G06F11/28 ,  G06F21/44 ,  G06F9/48 ,  G06F11/10

Abstract: Synchronization points are inserted into a program code to be monitored, and are associated with different branches resulting from execution of an indirect branch instruction. The synchronization points can be accessed by the monitored program code for the purpose of identifying which branch to use during execution of the indirect branch instruction of the monitored program code.

公开(公告)号：US20180300085A1

公开(公告)日：2018-10-18

申请号：US15900481

申请日：2018-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.

公开(公告)号：US10103721B2

公开(公告)日：2018-10-16

申请号：US15361594

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Michel Agoyan

IPC: H03K17/00 ,  H03K5/159 ,  H03K19/003 ,  G06F7/58 ,  H03K3/84 ,  H03K19/173

Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

公开(公告)号：US20180294313A1

公开(公告)日：2018-10-11

申请号：US16004195

申请日：2018-06-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/12

CPC classification number: H01L27/2409 ,  H01L27/1203 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

公开(公告)号：US20180269855A1

公开(公告)日：2018-09-20

申请号：US15700475

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez

IPC: H03H11/26

CPC classification number: H03H11/265 ,  G06F7/58 ,  H03K19/21 ,  H04L9/06

Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.

公开(公告)号：US20180268901A1

公开(公告)日：2018-09-20

申请号：US15984779

申请日：2018-05-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  H01L27/11521 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788 ,  H01L27/11526

CPC classification number: G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/7883

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

公开(公告)号：US20180247901A1

公开(公告)日：2018-08-30

申请号：US15698882

申请日：2017-09-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L23/00 ,  H01L29/06

CPC classification number: H01L23/573 ,  H01L23/576 ,  H01L29/0649

Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.

公开(公告)号：US10043741B2

公开(公告)日：2018-08-07

申请号：US15380894

申请日：2016-12-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: G01R31/26 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L21/66

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

公开(公告)号：US09998689B2

公开(公告)日：2018-06-12

申请号：US14557158

申请日：2014-12-01

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA

Inventor： David Coulon ,  Benoit Deschamps ,  Frederic Barbier

IPC: H01L21/00 ,  H04N5/345 ,  H01L27/146 ,  H04N5/378

CPC classification number: H04N5/345 ,  H01L27/14605 ,  H01L27/14647 ,  H01L27/14689 ,  H04N5/378

Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.