公开(公告)号：US20240188837A1

公开(公告)日：2024-06-13

申请号：US18063021

申请日：2022-12-07

Applicant: STMICROELECTRONICS, INC. ,  STMicroelectronics International N.V.

Inventor： Mahesh CHOWDHARY ,  Vijay KUMAR ,  Goldy ,  Kolin PAUL

IPC: A61B5/021 ,  A61B5/00 ,  A61B5/026 ,  A61B5/11

CPC classification number: A61B5/021 ,  A61B5/026 ,  A61B5/1102 ,  A61B5/6833 ,  A61B5/7267 ,  A61B5/7278 ,  A61B2562/0219 ,  A61B2562/043

Abstract: A blood pressure monitoring device includes a patch including two inertial measurement units placed adjacent to the skin of a user. The blood pressure monitoring device includes a control unit coupled to the patch and configured to receive sensor data from the inertial measurement units. The control unit includes an analysis model trained with multiple machine learning processes to generate blood pressure estimations based on the sensor data. A first general machine learning process trains the analysis model with a training set gathered from plurality of other individuals. The second general machine learning process retrains a portion of the analysis model with a second machine learning process utilizing individualized training set gathered from the user.

公开(公告)号：US20240178823A1

公开(公告)日：2024-05-30

申请号：US18516660

申请日：2023-11-21

Applicant: STMicroelectronics International N.V.

Inventor： Joran PANTEL ,  Daniel OLSON

IPC: H03K5/05

CPC classification number: H03K5/05

Abstract: A system-on-a-chip includes a first digital domain and a second digital domain. An interface circuit includes a level-shifting circuit for converting a signal between the first digital domain and the second digital domain. The first digital domain includes a control circuit configured to generate a control signal for transmission to the second digital domain. The control signal includes a pulse having a nominal duration adapted to the level-shifting circuit. At the input of the level-shifting circuit, the interface circuit includes, in the first domain, a conditional pulse-stretching circuit that lengthens a duration of the pulse of the control signal to at least the nominal duration when a duration of the pulse of the control signal is shorter than the nominal duration and non-zero.

公开(公告)号：US20240178179A1

公开(公告)日：2024-05-30

申请号：US18523007

申请日：2023-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Mauro MAZZOLA

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L24/40 ,  H01L23/49513 ,  H01L24/35 ,  H01L24/37 ,  H01L24/84 ,  H01L24/96 ,  H01L25/0655 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/3582 ,  H01L2224/37011 ,  H01L2224/40257 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/96 ,  H01L2924/182

Abstract: A semiconductor die is arranged at a die mounting location of an electrically conductive substrate. The electrically conductive substrate includes an array of electrically conductive leads having openings at the periphery of the electrically conductive substrate. An electrically conductive clip is arranged in a bridge-like position between the semiconductor die and an electrically conductive lead in the array of electrically conductive leads to provide electrical coupling therebetween. The electrically conductive clip has an end coupled to the electrically conductive lead, wherein the end includes: a planar proximal portion configured to contact the electrically conductive lead proximally of the openings, and a distal portion projecting beyond the proximal portion distally thereof, the distal portion provided with sculpturing configured to engage the openings to facilitate immobilizing the electrically conductive clip in the bridge-like position between the semiconductor chip and electrically conductive lead.

公开(公告)号：US20240178092A1

公开(公告)日：2024-05-30

申请号：US18505569

申请日：2023-11-09

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Gabriele BELLOCCHI ,  Simone RASCUNA' ,  Valeria PUGLISI

IPC: H01L23/31 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L23/3192 ,  H01L23/3171 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

Abstract: Electronic device, comprising: a solid body including a Silicon Carbide substrate, and further including an electrical terminal of the electronic device on the substrate; a passivation layer on the electrical terminal, of a first material; and a first adhesion improving layer coupled to the passivation layer and to the solid body, of a second material having predefined characteristics of adhesion to the first material, and configured to bond together the passivation layer and the solid body.

公开(公告)号：US20240176864A1

公开(公告)日：2024-05-30

申请号：US18521480

申请日：2023-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Xavier CHBANI ,  Nadia VAN-DEN-BOSSCHE

IPC: G06F21/44

CPC classification number: G06F21/44

Abstract: An electronic device includes a debug port providing a communications interface for debugging purposes, a plurality of processing unit access ports, an authentication interface circuit configured to authenticate the external device, and a further access port coupled between the debug port and the authentication interface circuit. The further access port is configured to be in an open state in which communications are relayed between the debug port and the authentication interface circuit. The authentication interface circuit has registers including a status register capable of being read by the external device via the debug port and the further access port, the status register being configured to store an indication of the open or closed state of each of the processing unit access ports.

公开(公告)号：US11984151B2

公开(公告)日：2024-05-14

申请号：US17850207

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

公开(公告)号：US11983025B2

公开(公告)日：2024-05-14

申请号：US17967498

申请日：2022-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Dhulipalla Phaneendra Kumar ,  Gourav Garg ,  Sourabh Banzal

IPC: G05F1/10 ,  G05F1/46 ,  G05F3/02 ,  H03K19/20

CPC classification number: G05F1/46 ,  H03K19/20

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

公开(公告)号：US11974419B1

公开(公告)日：2024-04-30

申请号：US18209018

申请日：2023-06-13

Applicant: STMicroelectronics International N.V.

Inventor： Florian Perminjat ,  Karine Saxod ,  Etienne Brosse

IPC: H05K9/00 ,  H01L23/552 ,  H01L31/167 ,  H01L23/60

CPC classification number: H05K9/0058 ,  H01L23/552 ,  H01L31/167 ,  H05K9/0084 ,  H05K9/0088 ,  H01L23/60

Abstract: Methods, systems, and apparatuses for electromagnetic shielding are provided, particularly for semiconductor packages and/or printed circuit boards. For example, an optical device covered by an RF can may be attached to a substrate. The RF can may have a first aperture for an optical path of the optical device. A deposition layer may provide electromagnetic shielding in conjunction with the RF can. The deposition layer may include one or more portions that are deposited at the same time, including a first portion with an aperture that narrows the aperture of the RF can. The deposition layer, after being deposited, may be cured. The deposition layer and RF can may provide electromagnetic shielding for the optical device.

公开(公告)号：US20240112728A1

公开(公告)日：2024-04-04

申请号：US18244782

申请日：2023-09-11

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Dipti ARYA ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  H03M1/12

Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.

公开(公告)号：US11933861B2

公开(公告)日：2024-03-19

申请号：US17860959

申请日：2022-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Sharad Gupta

IPC: G01R31/40

CPC classification number: G01R31/40

Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.