公开(公告)号：US10381344B2

公开(公告)日：2019-08-13

申请号：US15897524

申请日：2018-02-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L21/84 ,  H01L27/24 ,  H01L21/8249 ,  H01L29/732 ,  H01L45/00 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L29/08

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US20190244857A1

公开(公告)日：2019-08-08

申请号：US16384147

申请日：2019-04-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Didier DUTARTRE ,  Jean-Pierre CARRERE ,  Jean-Luc HUGUENIN ,  Clement PRIBAT ,  Sarah KUSTER

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/74 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76877 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/0649

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US20190235166A1

公开(公告)日：2019-08-01

申请号：US16374214

申请日：2019-04-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles BAUDOT

IPC: G02B6/125 ,  G02B6/122 ,  G02B6/136

CPC classification number: G02B6/125 ,  G02B6/1228 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/121 ,  G02B2006/12173 ,  G02B2006/12176

Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region which includes a bulge region. The bulge region is defined two successive etching operations using two distinct etch masks, where the first etching operation is a partial etch and the second etching operation is a complete etch.

公开(公告)号：US20190219847A1

公开(公告)日：2019-07-18

申请号：US16247096

申请日：2019-01-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane MONFRAY

IPC: G02F1/025

Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.

公开(公告)号：US10355041B2

公开(公告)日：2019-07-16

申请号：US15703251

申请日：2017-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US10321073B2

公开(公告)日：2019-06-11

申请号：US15358737

申请日：2016-11-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H04N5/353 ,  H04N5/378 ,  H04N5/372 ,  H01L27/146 ,  H04N5/363

Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.

公开(公告)号：US10302693B2

公开(公告)日：2019-05-28

申请号：US15468798

申请日：2017-03-24

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Chittoor Parthasarathy

IPC: G01R31/28

Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.

公开(公告)号：US20190137609A1

公开(公告)日：2019-05-09

申请号：US15805711

申请日：2017-11-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: G01S7/481 ,  H01L27/146 ,  G01S17/89 ,  G01S17/42

Abstract: A sensor array includes pixel kernels, wherein each pixel kernel includes RGB pixels, the RGB pixels being configured to provide a plurality of color signals, and Z pixels each having a single memory element, the Z pixels being configured to provide a single TOF signal. Each pixel kernel includes two to four Z pixels. The RGB and Z pixels can be integrated together on a single sensor array.

公开(公告)号：US20190113415A1

公开(公告)日：2019-04-18

申请号：US16211511

申请日：2018-12-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Philippe GROSSE ,  Patrick LE MAITRE ,  Jean-Francois CARPENTIER

IPC: G01M11/02 ,  G01R31/311 ,  G02B6/28 ,  G02B6/12 ,  G02B6/00 ,  G01R35/00 ,  G01R31/265 ,  G02B6/34 ,  G01R31/303 ,  G01R31/28 ,  G01R31/27 ,  G01R31/317

Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

公开(公告)号：US20190094107A1

公开(公告)日：2019-03-28

申请号：US16188537

申请日：2018-11-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01M11/00 ,  H04B10/07

Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.