公开(公告)号：US08810333B2

公开(公告)日：2014-08-19

申请号：US13234041

申请日：2011-09-15

Applicant: Claire Laporte ,  Hilal Ezzeddine

Inventor： Claire Laporte ,  Hilal Ezzeddine

IPC: H01P5/12 ,  H03H7/38

CPC classification number: H04B1/0064 ,  H04B1/0458 ,  H04B1/0483

Abstract: A multiband coupling circuit including: a number of paths equal to the number of frequency bands, each path having a first terminal and a second terminal; a third terminal and a fourth terminal; a number of distributed couplers equal to the number of paths, all couplers being identical and sized according to the highest frequency band, and each coupler including a first conductive line between first and second ports connected to the first and second terminals of the concerned path, and a second conductive line coupled to the first one between third and fourth ports; a first set of attenuations between the third ports of the couplers and the third terminal of the circuit; and an array of filters between the fourth ports of the coupler and the fourth terminal of the circuit.

Abstract translation: 一种多频带耦合电路，包括：多个等于频带数的路径，每个路径具有第一终端和第二终端; 第三终端和第四终端; 多个分布式耦合器等于路径数量，所有耦合器根据最高频带相同和大小，并且每个耦合器包括连接到相关路径的第一和第二端子的第一和第二端口之间的第一导线， 以及耦合到第三端口和第四端口之间的第一导线的第二导线; 耦合器的第三端口与电路的第三端子之间的第一组衰减; 以及耦合器的第四端口和电路的第四端子之间的滤波器阵列。

公开(公告)号：US20140217462A1

公开(公告)日：2014-08-07

申请号：US13762288

申请日：2013-02-07

Applicant: STMICROELECTRONICS (TOURS) SAS ,  UNIVERSITE FRANCOIS RABELAIS

Inventor： Samuel Menard ,  Gaël Gautier

IPC: H01L29/74 ,  H01L21/22

CPC classification number: H01L29/7424 ,  H01L29/0619 ,  H01L29/167 ,  H01L29/66386 ,  H01L29/747

Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.

Abstract translation: 一种高电压垂直功率元件，包括第一导电类型的硅衬底和从硅衬底的上表面延伸到硅衬底中的第二导电类型的第一半导体层，其中所述元件周边包括：多孔硅 环从上表面延伸到深度比第一层深的硅衬底; 以及从硅表面的下表面延伸到多孔硅环的第二导电类型的掺杂环。

公开(公告)号：US08698227B2

公开(公告)日：2014-04-15

申请号：US13332395

申请日：2011-12-21

Applicant: Yannick Hague ,  Samuel Menard

Inventor： Yannick Hague ,  Samuel Menard

IPC: H01L29/788

CPC classification number: H01L29/0638 ,  H01L21/70 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/747 ,  H01L29/87

Abstract: A mesa-type bidirectional Shockley diode delimited on its two surfaces by a peripheral groove filled with a glassivation including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of the regions of the first conductivity type, at the interface between the substrate and the corresponding layer of the second conductivity type, each buried region being complementary in projection with the other; and a peripheral ring under the external periphery of each of the glassivations, of same doping profile as the buried regions.

Abstract translation: 台面型双向Shockley二极管在其两个表面上由填充有玻璃化的外围槽限定，包括第一导电类型的衬底; 在基板的每一侧上具有第二导电类型的层; 在第二导电类型的每个层中的第一导电类型的区域; 在第一导电类型的每个区域下的第一导电类型的掩埋区域，在基板和第二导电类型的相应层之间的界面处，每个掩埋区域与另一个的突出互补; 以及在每个玻璃化的外围的外周环上，具有与掩埋区相同的掺杂分布。

公开(公告)号：US08648992B2

公开(公告)日：2014-02-11

申请号：US13938593

申请日：2013-07-10

Applicant: Mitsubishi Materials Corporation ,  STMicroelectronics(Tours) SAS

Inventor： Hideaki Sakurai ,  Toshiaki Watanabe ,  Nobuyuki Soyama ,  Guillaume Guegan

IPC: G02F1/1343

CPC classification number: H01L28/60 ,  B82Y30/00 ,  C04B35/4682 ,  C04B2235/3213 ,  C04B2235/441 ,  C04B2235/781 ,  C04B2235/785 ,  C04B2235/787 ,  H01G4/01 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02197 ,  H01L21/02282 ,  H01L28/55 ,  H01L28/65

Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.

Abstract translation: 薄膜电容器的特征在于形成下电极，在不施加温度大于300℃的退火工艺的情况下将组合物涂覆在下电极上，在从环境温度至500℃的范围内的预定温度下干燥 并在500〜800℃的范围内的预定温度下煅烧并高于干燥温度。 从涂覆到煅烧的过程进行从涂覆到煅烧一次或至少两次的过程，或者从涂覆到干燥的过程进行至少两次，然后进行一次煅烧。 在第一次煅烧后形成的电介质薄膜的厚度为20〜600nm。 初始煅烧步骤后形成的下部电极的厚度与电介质薄膜的厚度之比（下部电极的厚度/电介质薄膜的厚度）优选在0.10〜15.0的范围内。

公开(公告)号：US08604515B2

公开(公告)日：2013-12-10

申请号：US13105238

申请日：2011-05-11

Applicant: Benjamin Morillon

Inventor： Benjamin Morillon

IPC: H01L29/66

CPC classification number: H01L29/861 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/32 ,  H01L29/66098 ,  H01L2224/06181

Abstract: A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a second area of the first conductivity type on the external side of the epitaxial layer, in front of the first area, and implanted with the same dose as the first area, a first metallization covering the entire lower surface of the substrate, and a second metallization covering the second area.

Abstract translation: 形成在第一导电类型的半导体衬底中的双向保护部件，包括第一导电类型的第一注入区域，在衬底上的第二导电类型的外延层和第一注入区域，第一导电类型的第二区域 在外延层的外侧，在第一区域的前方，并以与第一区域相同的剂量注入覆盖基板的整个下表面的第一金属化和覆盖第二区域的第二金属化。

公开(公告)号：US08579995B2

公开(公告)日：2013-11-12

申请号：US12939502

申请日：2010-11-04

Applicant: Pierre Bouillon ,  Delphine Guy-Bouyssou

Inventor： Pierre Bouillon ,  Delphine Guy-Bouyssou

IPC: H01M6/46 ,  H01M4/82 ,  H01M6/00 ,  B23K26/00

CPC classification number: H01M4/0421 ,  H01M4/1395 ,  H01M4/1397 ,  H01M4/70 ,  H01M10/0562 ,  H01M10/0585 ,  Y10T29/49108 ,  Y10T29/49115

Abstract: A method for forming an integrated lithium-ion type battery, including the successive steps of: forming, on a substrate, a stack of a cathode layer made of a material capable of receiving lithium ions, an electrolyte layer, and an anode layer of the battery; forming a short-circuit between the anode and cathode layers; performing a thermal evaporation of lithium; and opening the short-circuit between the anode and cathode layers.

Abstract translation: 一种用于形成集成锂离子型电池的方法，包括以下连续步骤：在基板上形成由能够接收锂离子的材料制成的阴极层的叠层，电解质层和阳极层 电池; 在阳极和阴极层之间形成短路; 进行锂的热蒸发; 并打开阳极和阴极层之间的短路。

公开(公告)号：US08565695B2

公开(公告)日：2013-10-22

申请号：US12506708

申请日：2009-07-21

Applicant: Benoît Bonnet ,  Sylvain Charley ,  François Dupont

Inventor： Benoît Bonnet ,  Sylvain Charley ,  François Dupont

IPC: H04B1/02 ,  H04K3/00

CPC classification number: H01P5/18 ,  H03F1/02 ,  H03F3/24 ,  H03H7/40 ,  H04B1/0475 ,  H04B2001/045

Abstract: A method and a device for determining the amplitude and the phase of an impedance connected on a transmission line, including a bidirectional coupler having a first line interposed on the transmission line and having a second line providing at its respective ends two measurement signals, and a balun having its respective differential-mode inputs receiving data representative of the measurement signals.

Abstract translation: 一种用于确定连接在传输线上的阻抗的幅度和相位的方法和装置，包括一个双向耦合器，该双向耦合器具有插入在传输线上的第一条线路，并且具有在其两端提供两个测量信号的第二线路，以及 平衡 - 不平衡转换器具有各自的差分模式输入，接收表示测量信号的数据。

公开(公告)号：US08536682B2

公开(公告)日：2013-09-17

申请号：US12946992

申请日：2010-11-16

Applicant: Benjamin Morillon

Inventor： Benjamin Morillon

IPC: H01L29/861

CPC classification number: H01L29/8618 ,  H01L29/6609 ,  H01L29/66106 ,  H01L29/866

Abstract: A vertical bidirectional protection diode including, on a heavily-doped substrate of a first conductivity type, first, second, and third regions of the first, second, and first conductivity types, these regions all having a doping level greater than from 2 to 5×1019 atoms/cm3 and being laterally delimited by an insulated trench, each of these regions having a thickness smaller than 4 μm.

Abstract translation: 垂直双向保护二极管包括在第一导电类型的重掺杂衬底上的第一，第二和第一导电类型的第一，第二和第三区域，这些区域都具有大于2至5的掺杂水平 ×1019个原子/ cm3，并且由绝缘沟槽横向限定，这些区域中的每一个具有小于4μm的厚度。

公开(公告)号：US20130178017A1

公开(公告)日：2013-07-11

申请号：US13783529

申请日：2013-03-04

Applicant: STMicroelectronics (Tours) SAS

Inventor： Vincent Jarry ,  Patrick Hougron ,  Dominique Touzet ,  José Mendez

IPC: H01L21/683 ,  H01L21/78

CPC classification number: H01L21/683 ,  H01L21/67132 ,  H01L21/78 ,  Y10T29/41 ,  Y10T83/02 ,  Y10T225/393

Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.

Abstract translation: 一种用于从半导体晶片制造半导体芯片的方法，包括以下步骤：在第一支撑框架上紧固外部尺寸小于第一框架的外部尺寸并大于第一框架的内部尺寸的第二支撑框架 ; 将晶片布置在在第二框架上延伸的膜的表面上; 通过使用能够接收第一帧的设备进行晶片处理操作; 将第二框架与第一框架分离并移除第一框架; 并通过使用能够接收第二帧的设备进行晶片处理操作。

公开(公告)号：US20120267679A1

公开(公告)日：2012-10-25

申请号：US13448670

申请日：2012-04-17

Applicant: Samuel Menard

Inventor： Samuel Menard

IPC: H01L29/87 ,  H01L29/02

CPC classification number: H01L29/0626 ,  H01L27/0262 ,  H01L29/165 ,  H01L29/87

Abstract: A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region.

Abstract translation: 一种用于在半导体衬底的上表面中起始包括多孔硅层的半导体组件的结构。 该多孔硅层在其上表面侧通过金属化和在其下表面侧上被重掺杂的半导体区域接触。