SPDIF clock and data recovery with sample rate converter

    公开(公告)号:US09832012B2

    公开(公告)日:2017-11-28

    申请号:US15484408

    申请日:2017-04-11

    CPC classification number: H04L7/033 G06F13/4295 H04L7/0029 H04L7/02

    Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.

    RING NETWORK OF BLUETOOTH SPEAKERS
    58.
    发明申请

    公开(公告)号:US20170085989A1

    公开(公告)日:2017-03-23

    申请号:US15365795

    申请日:2016-11-30

    Abstract: A method for forming a complete ring network of a plurality of Bluetooth® speakers, the method including populating a configurable speaker register of each of the plurality of Bluetooth® speakers with an address of an upstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, populating the configurable speaker register of each of the plurality of Bluetooth® speakers with an address of a downstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, and coupling an audio source to one Bluetooth® speaker of the plurality of Bluetooth® speakers.

    Switched-Mode Audio Amplifier Employing Power-Supply Audio- Modulation
    59.
    发明申请
    Switched-Mode Audio Amplifier Employing Power-Supply Audio- Modulation 审中-公开
    开关式音频放大器采用电源音频调制

    公开(公告)号:US20140369529A1

    公开(公告)日:2014-12-18

    申请号:US13915805

    申请日:2013-06-12

    Abstract: A device and method are disclosed for modulating a power converter based on an audio signal to directly drive a speaker with a differential audio output signal. A first modulation signal and a second modulation signal are generated based on an input audio signal so that the first and second modulation signals are complementary signals to each other. In one embodiment, a feedback signal, such as an acoustic feedback signal from the speaker, is also used to generate the first and second modulation signals. A power supply voltage is modulated with the first modulation signal to generate a first voltage signal. The power supply voltage is also modulated with the second modulation signal to generate a second voltage signal. The first and second voltage signals form a differential audio signal that is used to drive the speaker. Alternatively, the power converter can drive a speaker with a single-ended output signal.

    Abstract translation: 公开了一种用于基于音频信号调制功率转换器以直接驱动具有差分音频输出信号的扬声器的装置和方法。 基于输入音频信号生成第一调制信号和第二调制信号,使得第一和第二调制信号彼此互补。 在一个实施例中,诸如来自扬声器的声反馈信号的反馈信号也用于产生第一和第二调制信号。 用第一调制信号调制电源电压以产生第一电压信号。 电源电压也用第二调制信号进行调制以产生第二电压信号。 第一和第二电压信号形成用于驱动扬声器的差分音频信号。 或者,功率转换器可以驱动具有单端输出信号的扬声器。

    SPDIF Clock and Data Recovery With Sample Rate Converter
    60.
    发明申请
    SPDIF Clock and Data Recovery With Sample Rate Converter 有权
    SPDIF采样速率转换器的时钟和数据恢复

    公开(公告)号:US20140270028A1

    公开(公告)日:2014-09-18

    申请号:US13800557

    申请日:2013-03-13

    CPC classification number: H04L7/027 G06F13/4295 H04L7/0029 H04L7/02

    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

    Abstract translation: 用于从输入数据流中恢复数据而不输入输入采样电路与输入数据流的同步的系统和技术确定输入采样(或帧)的计数,而不产生频率锁定到输入数据流的信号。 产生包括大于或等于输入数据流的预期频率的频率的第一时钟。 响应于在输入数据流中接收到的采样,采样计数递增,并且响应于第二时钟信号递减。 如果采样计数器的采样计数不等于预定采样计数值,并且如果采样计数等于预定采样计数值则阻塞第一时钟信号,则通过传递第一时钟信号来产生第二时钟信号。

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