公开(公告)号：US20200295017A1

公开(公告)日：2020-09-17

申请号：US16298413

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien FROUGIER ,  Ruilong XIE

IPC: H01L27/11514 ,  H01L49/02 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode.

公开(公告)号：US20200286900A1

公开(公告)日：2020-09-10

申请号：US16295485

申请日：2019-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

公开(公告)号：US20200279783A1

公开(公告)日：2020-09-03

申请号：US16288152

申请日：2019-02-28

Applicant: GLOBALFOUNDRIES INC. ,  NOVA MEASURING INSTRUMENTS LTD.

Inventor： PADRAIG TIMONEY ,  TAHER KAGALWALA ,  ALOK VAID ,  SRIDHAR MAHENDRAKAR ,  DHAIRYA DIXIT ,  SHAY YOGEV ,  MATTHEW SENDELBACH ,  CHARLES KANG

IPC: H01L21/66 ,  G01N21/956 ,  H01L29/66 ,  G01N21/95

Abstract: Process control during manufacture of semiconductor devices by collecting scatterometric spectra of a FinFET reference fin structure on a reference semiconductor wafer at a first checkpoint proximate to a first processing step during fabrication of the reference semiconductor wafer, collecting reference measurements of the reference fin structure at a second checkpoint proximate to a second processing step subsequent to the first checkpoint, and performing machine learning to identify correspondence between the scatterometric spectra and values based on the reference measurements and train a prediction model for producing a prediction value associated with a corresponding production fin structure of the FinFET on a production semiconductor wafer based on scatterometric spectra of the production fin structure collected at the corresponding first checkpoint during fabrication of the production semiconductor wafer.

公开(公告)号：US10763342B2

公开(公告)日：2020-09-01

申请号：US16216356

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US10763328B2

公开(公告)日：2020-09-01

申请号：US16151938

申请日：2018-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Omur Isil Aydin ,  Judson Holt ,  Lakshmanan Vanamurthy ,  Tobias Heyne ,  Pei-Yu Chou ,  Cäcilia Brantz

IPC: H01L29/08 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L21/02 ,  H01L21/265 ,  H01L29/167

Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. A first epitaxial layer has a first surface and a second surface inclined relative to the first surface. A surface layer is arranged on the first and second surfaces of the first epitaxial layer. A second epitaxial layer is arranged over the surface layer on the first and second surfaces of the first epitaxial layer. A portion of the first epitaxial layer defines an interface with the surface layer. The portion of the first epitaxial layer contains a first concentration of a dopant. The surface layer contains a second concentration of the dopant that is greater than the first concentration of the dopant in the portion of the first epitaxial layer.

公开(公告)号：US20200273953A1

公开(公告)日：2020-08-27

申请号：US16287365

申请日：2019-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Chu ,  Wei Ma ,  Jae Gon Lee ,  Hong Yu ,  Zhenyu Hu ,  Srikanth Balaji Samavedam

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: One illustrative integrated circuit product disclosed herein includes a short-channel transistor device and a long-channel transistor device formed above a semiconductor substrate, wherein a first gate structure for the short-channel transistor device includes a short-channel WFM layer with a first upper surface that is positioned at a first distance above an upper surface of the semiconductor substrate, and wherein a second gate structure for the long-channel transistor device includes a long-channel WFM layer with a second upper surface that is positioned at a second distance above the upper surface of the semiconductor substrate, wherein the first distance is greater than the second distance.

公开(公告)号：US20200266286A1

公开(公告)日：2020-08-20

申请号：US16280343

申请日：2019-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoming Yang ,  Sipeng Gu ,  Jeffrey Chee ,  Keith H. Tabakman

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.

公开(公告)号：US10749031B2

公开(公告)日：2020-08-18

申请号：US15273778

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

公开(公告)号：US10747254B1

公开(公告)日：2020-08-18

申请号：US16558599

申请日：2019-09-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sher Jiun Fang ,  See Taur Lee

IPC: G05F3/24 ,  H03K17/14 ,  G05F3/26

Abstract: The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor.

公开(公告)号：US10734525B2

公开(公告)日：2020-08-04

申请号：US15920886

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Christopher M. Prindle ,  Nigel G. Cave

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.