公开(公告)号：US07170125B2

公开(公告)日：2007-01-30

申请号：US10724134

申请日：2003-12-01

Applicant: Harald Seidl ,  Martin Gutsche

Inventor： Harald Seidl ,  Martin Gutsche

IPC: H01L29/72

CPC classification number: H01L28/65 ,  H01L27/10861 ,  H01L29/66181 ,  H01L29/94 ,  H01L29/945 ,  Y10S257/906 ,  Y10S257/924

Abstract: A method for patterning layers made of ruthenium or ruthenium(IV) oxide and a capacitor comprising at least one electrode which is constructed from ruthenium or ruthenium(IV) oxide at least in sections. A layer made of ruthenium or ruthenium(IV) oxide is deposited on a substrate and said layer is subsequently covered with a covering layer at least in sections. Through heat treatment of the construction thus obtained in an oxygen atmosphere, the ruthenium is converted into RuO4 in the uncovered sections and removed by sublimation. The method enables the simple patterning of layers made of ruthenium or ruthenium(IV) oxide and the construction of complex structures, such as trench capacitors, for example.

Abstract translation: 用于对由钌或钌（IV）氧化物制成的层的图案的方法和包括至少一个由氧化钌或氧化钌（IV）构成的至少一个电极的电容器。 由氧化钌或钌（IV）制成的层被沉积在衬底上，并且所述层随后至少以部分覆盖覆盖层。 通过在氧气氛中对由此获得的结构进行热处理，将钌转化成未覆盖部分中的RuO 4，并通过升华除去。 该方法使得能够简单地构图由钌或钌（IV）氧化物制成的层，以及例如诸如沟槽电容器的复杂结构的构造。

公开(公告)号：US20070012956A1

公开(公告)日：2007-01-18

申请号：US11182022

申请日：2005-07-14

Applicant: Martin Gutsche ,  Harald Seidl ,  Franz Kreupl

Inventor： Martin Gutsche ,  Harald Seidl ,  Franz Kreupl

IPC: H01L29/768

CPC classification number: B82Y10/00 ,  G11C13/0004 ,  G11C13/025 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.

Abstract translation: 存储单元包括在第一电极和第二电极之间包括纳米线，第二电极和相变材料的第一电极。

公开(公告)号：US07138677B2

公开(公告)日：2006-11-21

申请号：US10787934

申请日：2004-02-27

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L27/108

CPC classification number: H01L29/66181 ,  H01L29/945

Abstract: Arrangement of capacitors which, without taking up an additional area in the semiconductor substrate, have an increased capacitance compared with conventional capacitors in DRAM memory cells. The arrangement of capacitors according to the invention is based on a combination of two or more separately arranged individual capacitors in or on a substrate to form two or more capacitors arranged one in the other or one above the other. In this case, an outer capacitor encloses at least one or a plurality of inner. capacitors or a substantial part of an upper capacitor lies above a lower capacitor. A method for fabricating the arrangement of capacitors also is described.

Abstract translation: 与DRAM存储单元中的常规电容器相比，不占据半导体衬底中的附加区域的电容器的布置具有增加的电容。 根据本发明的电容器的布置基于在衬底中或衬底上的两个或更多个单独布置的单独电容器的组合，以形成一个或另一个彼此排列的两个或更多个电容器。 在这种情况下，外部电容器包围至少一个或多个内部。 电容器或大部分上部电容器位于较低电容器的上方。 还描述了制造电容器布置的方法。

公开(公告)号：US07122423B2

公开(公告)日：2006-10-17

申请号：US11055431

申请日：2005-02-10

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/8242

CPC classification number: H01L27/1087

Abstract: The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate (101), which forms a first electrode, a trench-like recess (102) etched into the substrate (101), conductive material, which is provided as a projection in a central region of the trench-like recess (102) and spaced apart from the side walls (107) of the trench-like recess (102) and is in electrical contact with the substrate at the base (104) of the trench-like recess (102), a dielectric layer (108), which has been deposited on the side walls (107) of the trench-like recess (102), the base (104) of the trench-like recess (102) and the surfaces of the conductive material (105), and an electrode layer (110), which has been deposited on the dielectric layer (108) and forms a second electrode.

Abstract translation: 本发明提供了一种用于制造用于存储电荷的存储单元的方法，该方法具有形成第一电极的基板（101），蚀刻到基板（101）中的沟槽状凹部（102），导电材料 设置为在所述沟槽状凹部（102）的中心区域中并与所述沟槽状凹部（102）的侧壁（107）间隔开并且与所述基底（104）处的所述基板电接触的突起， 已经沉积在沟槽状凹部（102）的侧壁（107）上的电介质层（108），沟槽状凹部（102）的基底（104） 102）和导电材料（105）的表面以及已经沉积在电介质层（108）上并形成第二电极的电极层（110）。

公开(公告)号：US07084454B2

公开(公告)日：2006-08-01

申请号：US10950477

申请日：2004-09-28

Applicant: Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

Inventor： Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

IPC: H01L29/76

CPC classification number: H01L21/28282 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S438/954

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

Abstract translation: 非易失性集成半导体存储器具有具有隧道势垒层和电荷存储电平的层的排列。 电荷储存电平具有在空间固定位置中分散存储在电荷载体中的电介质材料。 隧道势垒层具有高能电荷载流子穿过的材料。 电荷存储水平的至少一个界面表面具有比远离电荷存储水平的隧道势垒层的界面更大的微观粗糙度。 电荷存储水平在第一区域中具有比在第二区域中更大的层厚度。 这在横向方向产生正电荷载体和负电荷载体的相对相同的分布和定位。 因此，分散到电荷存储电平的电荷载体完全复合，从而降低了在非易失性存储器的长期操作期间不可预见的数据丢失的风险。

公开(公告)号：US20060035430A1

公开(公告)日：2006-02-16

申请号：US11191461

申请日：2005-07-28

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L29/66181

Abstract: The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation collar (10) in the upper trench region as far as the top side of the silicon substrate (1); depositing a layer (12) made of a metal oxide in the trench (5); carrying out a thermal treatment for selectively reducing the layer (12), a region of the layer (12) that lies below the insulation collar (10) above the silicon substrate (1) being reduced and being converted into a first capacitor electrode layer (15) made of a corresponding metal silicide, and a region of the layer (12) that lies above the insulation collar (10) not being reduced; selectively removing the non-reduced region of the layer (12) that lies above the insulation collar (10); providing a capacitor dielectric layer (18) in the trench (5) above the first capacitor electrode layer (15); and providing a second capacitor electrode layer (20) in the trench (5) above the capacitor dielectric layer (18).

Abstract translation: 本发明提供一种在硅衬底（1）中具有绝缘套环（10）的沟槽电容器的制造方法，其具有以下步骤：在硅衬底（1）中提供沟槽（5）; 在所述上沟槽区域中提供所述绝缘套环（10）直到所述硅衬底（1）的顶侧; 在沟槽（5）中沉积由金属氧化物制成的层（12）; 进行用于选择性地还原层（12）的热处理，位于硅衬底（1）上方的绝缘套环（10）下方的层（12）的区域被还原并被转换成第一电容器电极层 15），并且位于所述绝缘套环（10）上方的所述层（12）的不被还原的区域; 选择性地去除位于绝缘套环（10）上方的层（12）的非还原区域; 在第一电容器电极层（15）上方的沟槽（5）中提供电容器介电层（18）; 以及在电容器介电层（18）上方的沟槽（5）中提供第二电容器电极层（20）。

公开(公告)号：US06977405B2

公开(公告)日：2005-12-20

申请号：US10792742

申请日：2004-03-05

Applicant: Jörn Lützen ,  Bernd Goebel ,  Dirk Schumann ,  Martin Gutsche ,  Harald Seidl ,  Martin Popp ,  Alfred Kersch ,  Werner Steinhögl

Inventor： Jörn Lützen ,  Bernd Goebel ,  Dirk Schumann ,  Martin Gutsche ,  Harald Seidl ,  Martin Popp ,  Alfred Kersch ,  Werner Steinhögl

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract translation: 为了制造半导体存储器，在第一沟槽中布置有沟槽电容器。 在第一沟槽的旁边，在衬底中布置有第一纵向沟槽，并且在第一沟槽的另一侧平行的第二纵向沟槽。 第一间隔字线布置在第一纵向沟槽中，第二间隔字线布置在第二纵向沟槽中。 布置在第一沟槽中，连接腹板之间的第一隔离物字线和第二隔离物字线之间的厚度，该厚度在第一隔离物字线的方向上小于第一沟槽的方向上的宽度的一半 的第一个间隔字线。

公开(公告)号：US20050258510A1

公开(公告)日：2005-11-24

申请号：US11125654

申请日：2005-05-10

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/08 ,  H01L29/76

CPC classification number: H01L28/56 ,  H01L21/022 ,  H01L21/31604 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

Abstract: The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive element (100), the substrate (101) provided as an electrode layer is conditioned, a dielectric layer (102) is deposited on the conditioned substrate (101) and a second electrode layer (104) is applied on the layer stack produced, the layer stack being modified by a heat treatment in such a way that the dielectric layer (102) deposited on the conditioned substrate (101) forms a dielectric mixed layer (105) with a reaction layer (103) deposited on the dielectric layer (102), which dielectric mixed layer has an increased dielectric constant (k) or an increased thermal stability.

Abstract translation: 本发明提供一种电容元件（100）的制造方法，设置有作为电容元件（100）的第一电极层的基板（101），将作为电极层设置的基板（101）进行调理， 层（102）沉积在经调理的基底（101）上，并且第二电极层（104）被施加在所产生的层叠层上，通过热处理改变层堆叠，使得介电层（102）沉积 在调理衬底（101）上形成电介质混合层（105），其上沉积有介电层（102）上的反应层（103），该电介质混合层具有增加的介电常数（k）或增加的热稳定性。

公开(公告)号：US20050245022A1

公开(公告)日：2005-11-03

申请号：US11112940

申请日：2005-04-22

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108

CPC classification number: H01L27/10817 ,  H01L27/10814 ,  H01L28/90

Abstract: The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are mechanically stabilized.

Abstract translation: 本发明涉及叠层电容器阵列和叠层电容器阵列的制造方法，所述层叠电容器阵列具有多个层叠的电容器，绝缘体保持至少两个彼此间隔开的相邻叠层电容器，使得它们之间不会发生电接触， 电容器机械稳定。

公开(公告)号：US20050205917A1

公开(公告)日：2005-09-22

申请号：US11071536

申请日：2005-03-04

Applicant: Harald Seidl

Inventor： Harald Seidl

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L29/66181 ,  H01L29/945

Abstract: The present invention provides a trench capacitor, in particular for use in a semiconductor memory cell, having a trench (5) formed in a semiconductor substrate (1); an insulation collar (3) in the upper region of the trench (5); a first conductive capacitor electrode (1a) situated in the trench (5) or in the semiconductor substrate (1); a conductive second capacitor electrode (10, 25, 30), situated in the trench (5), has a lower nonmetallic part (10) and an upper metallic part (30), the upper metallic part (30) extending right into the region between the insulation collar (3); a dielectric layer (4) as capacitor dielectric situated between the first and second capacitor electrodes (1a; 10, 25, 30). A part (25) made of a metal silicide is situated between the lower nonmetallic part (10) and the upper metallic part (30). The invention likewise provides a corresponding fabrication method.

Abstract translation: 本发明提供了一种特别用于半导体存储单元的沟槽电容器，其具有在半导体衬底（1）中形成的沟槽（5）; 在沟槽（5）的上部区域中的绝缘套环（3）; 位于沟槽（5）或半导体衬底（1）中的第一导电电容器电极（1a）; 位于沟槽（5）中的导电的第二电容器电极（10,25,30）具有下部非金属部分（10）和上部金属部分（30），上部金属部分（30）向右延伸到该区域 绝缘环（3）之间; 位于所述第一和第二电容器电极（1a; 10,25,30）之间的作为电容器电介质的电介质层（4）。 由金属硅化物制成的部分（25）位于下部非金属部分（10）和上部金属部分（30）之间。 本发明同样提供了相应的制造方法。