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    Semiconductor memory device
    55.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07643364B2

    公开(公告)日：2010-01-05

    申请号：US12004291

    申请日：2007-12-20

    Applicant: Jong-Cheol Lee ,  Myeong-O Kim

    Inventor： Jong-Cheol Lee ,  Myeong-O Kim

    IPC: G11C7/00

    CPC classification number: G11C7/08 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

    Abstract: A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed. The semiconductor memory device includes a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.

    Abstract translation: 一种半导体存储器件，包括位线读出放大器，用于放大与存储在存储单元的电容器中的电荷相对应的电压并输出放大电压;以及I / O读出放大器，用于接收位线读出放大器的输出，放大 公开了输出的电压电平并输出放大的电压电平。 半导体存储器件包括读出放大使能信号控制部分，其接收初始读出放大使能信号，将初始读出放大使能信号顺序地延迟多个预定时间周期，并且选择性地输出多个延迟读出放大使能信号， 半导体存储器件的操作速度和制造成品率; 多个时钟读出放大器，其各自接收I / O读出放大器的输出信号，响应于多个延迟读出放大使能信号中的每一个放大I / O读出放大器的输出信号，并依次输出输出 电源电压信号或接地电压电平响应; 以及前级输出驱动电路，其依次接收多个时钟读出放大器的输出信号，将多个时钟读出放大器的输出信号延迟预定的时间周期，然后截取时钟感测放大器的输出 前一步。

    Capacitor of semiconductor device and method of fabricating the same
    57.
    发明授权
    Capacitor of semiconductor device and method of fabricating the same 有权
    半导体器件的电容器及其制造方法

    公开(公告)号：US07442981B2

    公开(公告)日：2008-10-28

    申请号：US11316487

    申请日：2005-12-21

    Applicant: Gab-Jin Nam ,  Young-Sun Kim ,  Cha-Young Yoo ,  Jong-Cheol Lee ,  Jin-Tae Noh ,  Jae-Young Ahn ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo

    Inventor： Gab-Jin Nam ,  Young-Sun Kim ,  Cha-Young Yoo ,  Jong-Cheol Lee ,  Jin-Tae Noh ,  Jae-Young Ahn ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L28/75 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.

    Abstract translation: 提供一种半导体器件的电容器及其制造方法。 在一个实施例中，电容器包括形成在半导体衬底上的下电极; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 上电极包括依次堆叠的第一导电层，第二导电层和第三导电层。 第一导电层包括金属层，导电金属氧化物层，导电金属氮化物层或导电金属氮氧化物层。 第二导电层包括掺杂多晶硅锗层。 第三导电层包括具有比第二导电层的电阻低的电阻的材料。

    Method and circuit for writing double data rate (DDR) sampled data in a memory device
    58.
    发明授权
    Method and circuit for writing double data rate (DDR) sampled data in a memory device 失效
    用于在存储器件中写入双倍数据速率（DDR）采样数据的方法和电路

    公开(公告)号：US07295489B2

    公开(公告)日：2007-11-13

    申请号：US11037602

    申请日：2005-01-18

    Applicant: Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

    Inventor： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

    IPC: G11C7/00

    CPC classification number: G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

    Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

    Abstract translation: 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。

    Semiconductor memory device with hierarchical bit line structure
    59.
    发明申请
    Semiconductor memory device with hierarchical bit line structure 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US20070115710A1

    公开(公告)日：2007-05-24

    申请号：US11480447

    申请日：2006-07-05

    Applicant: Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    Inventor： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC: G11C5/06

    CPC classification number: G11C11/417 ,  G11C7/18 ,  G11C8/12

    Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    Abstract translation: 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

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