公开(公告)号：US20090207666A1

公开(公告)日：2009-08-20

申请号：US12428062

申请日：2009-04-22

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/349 ,  G11C16/3495

摘要： Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

摘要翻译： 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

公开(公告)号：US07518909B2

公开(公告)日：2009-04-14

申请号：US11606908

申请日：2006-12-01

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.

摘要翻译： 非挥发性半导体存储器件包括第一和第二子存储器阵列和布置在第一和第二子存储器阵列之间的捆扎线。 通过同时向连接到第一子存储器阵列内的存储单元的奇偶位线施加编程电压来执行第一子存储器阵列的编程操作。

公开(公告)号：US07510963B2

公开(公告)日：2009-03-31

申请号：US10989930

申请日：2004-11-16

申请人： Won-suk Yang ,  Ki-nam Kim ,  Hong-sik Jeong

发明人： Won-suk Yang ,  Ki-nam Kim ,  Hong-sik Jeong

IPC分类号： H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.

摘要翻译： 半导体器件及其制造方法包括半导体衬底，形成在半导体衬底上的层间电介质层（ILD）层，形成在ILD层中的第一接触柱，具有与ILD层的表面相邻的入口部分的宽度 大于邻近半导体衬底的接触部分的宽度;以及第二接触柱，其与第一接触螺柱间隔开并形成在ILD层中。 半导体器件还包括形成在ILD层上的接合焊盘，其接触第二接触柱的表面，其宽度大于第二接触柱的宽度。 第二接触柱具有与入口部相同的接触部的宽度。 此外，在着陆焊盘的侧壁上形成至少一个包括蚀刻阻挡材料的间隔物，并且在着陆焊盘上形成蚀刻停止层。 第一接触柱的入口部分的宽度比接触部分的宽度大30-60％。

公开(公告)号：US20080111121A1

公开(公告)日：2008-05-15

申请号：US11855952

申请日：2007-09-14

申请人： Jae-Hoon JANG ,  Ki-Nam KIM ,  Soon-Moon JUNG

发明人： Jae-Hoon JANG ,  Ki-Nam KIM ,  Soon-Moon JUNG

IPC分类号： H01L47/00

CPC分类号： G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L45/1683 ,  Y10S257/91

摘要： A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

摘要翻译： 公开了一种相变存储器件及其制造方法。 相变存储器件包括具有第一导电类型和侧壁的第一导体图案。 第二导体图案连接到第一导体图案的侧壁以形成二极管。 相变层电连接到第二导体图案，顶电极连接到相变层。

公开(公告)号：US20060160295A1

公开(公告)日：2006-07-20

申请号：US11370454

申请日：2006-03-07

申请人： Ji-young Kim ,  Ki-nam Kim

发明人： Ji-young Kim ,  Ki-nam Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/761 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.

公开(公告)号：US07057238B2

公开(公告)日：2006-06-06

申请号：US10452034

申请日：2003-05-30

申请人： Ji-young Kim ,  Ki-nam Kim

发明人： Ji-young Kim ,  Ki-nam Kim

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/761 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.

公开(公告)号：US20060108622A1

公开(公告)日：2006-05-25

申请号：US11248629

申请日：2005-10-12

申请人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

发明人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

IPC分类号： H01L29/94 ,  H01L21/00

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

公开(公告)号：US20060006447A1

公开(公告)日：2006-01-12

申请号：US11180954

申请日：2005-07-12

申请人： Hyun-Ho Kim ,  Heung-Jin Joo ,  Ki-Nam Kim

发明人： Hyun-Ho Kim ,  Heung-Jin Joo ,  Ki-Nam Kim

IPC分类号： H01L27/108

CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/91

摘要： A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer on an inner sidewall of an opening exposing the plate electrode by a plasma entire surface anisotropic etching.

公开(公告)号：US06961271B2

公开(公告)日：2005-11-01

申请号：US10620022

申请日：2003-07-14

申请人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

发明人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

IPC分类号： G11C11/409 ,  G11C5/06 ,  G11C11/404 ,  G11C11/405 ,  G11C7/00

CPC分类号： G11C11/405 ,  G11C11/404

摘要： A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

摘要翻译： 存储单元阵列块具有由存储单元对构成的单元存储单元，每个存储单元具有存储单元和补充存储单元。 第二单元存储单元与第一单元存储单元进行交织，第四单元存储单元与第三单元存储单元交错。 第一和第二读出放大器分别设置在阵列块的上方和下方。 第一开关将与第一单元存储单元耦合的位线与第一读出放大器连接，并将与第二单元存储单元耦合的位线与第二读出放大器相连接。 第二开关将与第三单元存储单元耦合的位线与第一读出放大器连接，并将与第四单元存储单元耦合的位线连接到第二读出放大器。 选择的单元存储单元选择性地与读出放大器连接，减少读出放大器的数量。

公开(公告)号：US06929997B2

公开(公告)日：2005-08-16

申请号：US10113622

申请日：2002-04-02

申请人： Dong-Jin Jung ,  Ki-Nam Kim

发明人： Dong-Jin Jung ,  Ki-Nam Kim

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L21/8242

CPC分类号： H01L27/11502 ,  H01L21/31604 ,  H01L21/3162 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

摘要： Disclosed is a triple metal line 1T/1C ferroelectric memory device and a method to make the same. A ferroelectric capacitor is connected to the transistor through a buried contact plug. An oxidation barrier layer lies between the contact plug and the lower electrode of the capacitor. A diffusion barrier layer covers the ferroelectric capacitor to prevent diffusion of material into or out of capacitor. As a result of forming the oxidation barrier layer, the contact plug is not exposed to the ambient oxygen atmosphere thereby providing a reliable ohmic contact between the contact plug and the lower electrode. Also, the memory device provides a triple interconnection structure made of metal, which improves device operation characteristics.

摘要翻译： 公开了三金属线1T / 1C铁电存储器件及其制造方法。 铁电电容器通过埋入式接触插头连接到晶体管。 氧化阻挡层位于电容器的接触插塞和下电极之间。 扩散阻挡层覆盖铁电电容器以防止材料扩散进入或流出电容器。 作为形成氧化阻挡层的结果，接触塞不暴露于环境氧气氛中，从而在接触塞和下电极之间提供可靠的欧姆接触。 此外，存储器件提供由金属制成的三重互连结构，这提高了器件操作特性。