Method of manufacturing low resistance and low junction leakage contact
    51.
    发明授权
    Method of manufacturing low resistance and low junction leakage contact 失效
    制造低电阻和低结漏电接触的方法

    公开(公告)号:US5899741A

    公开(公告)日:1999-05-04

    申请号:US40432

    申请日:1998-03-18

    Abstract: A new method of forming an amorphous silicon glue layer in the formation of a contact is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. An amorphous silicon layer is deposited overlying the insulating layer and within the opening. Ions are implanted into the amorphous silicon layer whereby grain sizes within the amorphous silicon layer are reduced. Native oxide on the surface of the amorphous silicon layer is removed. A titanium/titanium nitride layer is deposited overlying the amorphous silicon layer. A metal layer is deposited overlying the titanium/titanium nitride layer and filling the opening. The substrate is annealed whereby the titanium layer reacts with the amorphous silicon layer and the silicon semiconductor substrate to form titanium silicide. The metal layer is etched back or patterned to complete metallization in the fabrication of an integrated circuit device.

    Abstract translation: 描述了在形成接触时形成非晶硅胶层的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 绝缘层沉积在半导体器件结构上。 通过绝缘层蚀刻开口以接触半导体器件结构之一。 非晶硅层沉积在绝缘层上并且在开口内。 将离子注入到非晶硅层中,由此减小非晶硅层内的晶粒尺寸。 去除非晶硅层表面上的天然氧化物。 覆盖在非晶硅层上的钛/氮化钛层被沉积。 沉积覆盖在钛/氮化钛层上并填充开口的金属层。 将衬底退火,由此钛层与非晶硅层和硅半导体衬底反应形成硅化钛。 金属层被回蚀或图案化以在集成电路器件的制造中完成金属化。

    Method for manufacturing a fuse structure
    52.
    发明授权
    Method for manufacturing a fuse structure 失效
    熔丝结构的制造方法

    公开(公告)号:US5652175A

    公开(公告)日:1997-07-29

    申请号:US684071

    申请日:1996-07-19

    CPC classification number: H01L23/5258 H01L2924/0002 Y10S148/055

    Abstract: A fuse structure is described in which a metallic frame is inserted between the insulation layers, through which the fuse window passes, and the final passivation layer. This frame is used as a mask during fuse window formation so alignment is simplified and problems arising from the presence of insulating residues on the surface of the fuse window layer are avoided.

    Abstract translation: 描述了一种熔丝结构,其中金属框架插入在熔丝窗通过的绝缘层和最终钝化层之间。 在保险丝窗口形成期间,该框架用作掩模,因此简化了对准,并避免了在熔丝窗口层的表面上存在绝缘残留物所引起的问题。

    Process for formation of epitaxial cobalt silicide and shallow junction
of silicon
    53.
    发明授权
    Process for formation of epitaxial cobalt silicide and shallow junction of silicon 失效
    在硅上形成外延钴硅化物和浅结的工艺

    公开(公告)号:US5536684A

    公开(公告)日:1996-07-16

    申请号:US269440

    申请日:1994-06-30

    Abstract: A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer. If the cobalt silicide layer after the ion implantation contain dopants, then during the anneal the dopants are driven out of the cobalt silicide layer and diffuse into the silicon substrate to form a conformal shallow junction. The resulting structure can be used in the vertical integration of microelectronic devices. In other words, the resulting structure is suitable for growing selective epitaxial silicon, for growing epitaxial insulators, for processing devices above the silicide in that epitaxial silicon, and for processing devices with buried conductors.

    Abstract translation: 用于形成平面外延钴硅化物并形成用于半导体处理的浅共形结的方法。 形成硅化钴和氮化钛双层。 化学去除氮化钛层。 然后将具有或不具有掺杂剂的离子注入到硅化钴层中。 在离子注入期间,将至少一部分硅化钴层转变为无定形钴硅混合物,而非非晶部分保持单晶。 如果离子注入包含掺杂剂,则在注入完成之后,硅化钴层的非晶态部分和非非晶部分均含有掺杂剂。 然后将衬底在包含氮气的环境中或在氧化环境中退火。 在退火期间,硅衬底的非晶部分再结晶成单晶硅化钴层。 如果离子注入后的硅化钴层含有掺杂剂,则在退火期间,掺杂剂被驱出钴硅化物层并扩散到硅衬底中以形成共形的浅结。 所得结构可用于微电子器件的垂直集成。 换句话说,所得结构适于生长选择性外延硅,用于生长外延绝缘体,用于在该外延硅中的硅化物上方处理器件,以及用于处理具有埋入导体的器件。

    POINT CLOUD ATTRIBUTE ENCODING METHOD, DECODING METHOD, ENCODING DEVICE, AND DECODING DEVICE

    公开(公告)号:US20230419554A1

    公开(公告)日:2023-12-28

    申请号:US18252872

    申请日:2020-11-27

    CPC classification number: G06T9/001 G06T9/40

    Abstract: A point cloud attribute encoding method, a decoding method, an encoding device and a decoding device are disclosed, the point cloud attribute encoding method including: constructing an N-layer binary tree by partitioning a target point cloud according to positions of points within the point cloud, N being an integer greater than 1; for a target node at layer P of the binary tree, obtaining child nodes of the target node, determining a first attribute coefficient and second attribute coefficients of the target node by transforming first attribute coefficients of the child nodes, P being an integer greater than or equal to 1 and less than or equal to N−1; using the first attribute coefficient of a root node and the second attribute coefficients of each target node in the binary tree as output coefficients of the point cloud attribute encoding method.

    INTERRUPTION OF PROGRAM OPERATIONS AT A MEMORY SUB-SYSTEM

    公开(公告)号:US20230014869A1

    公开(公告)日:2023-01-19

    申请号:US17943113

    申请日:2022-09-12

    Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.

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