公开(公告)号：US20080195849A1

公开(公告)日：2008-08-14

申请号：US11705987

申请日：2007-02-14

Applicant: Antonio Gonzalez ,  Josep M. Codina ,  Pedro Lopez ,  Fernando Latorre ,  Jose-Alejandro Pineiro ,  Enric Gibert ,  Jaume Abella ,  Jaideep Moses ,  Donald Newell ,  Ravishankar Iyer ,  Ramesh G. Illikkal ,  Srihari Makineni

Inventor： Antonio Gonzalez ,  Josep M. Codina ,  Pedro Lopez ,  Fernando Latorre ,  Jose-Alejandro Pineiro ,  Enric Gibert ,  Jaume Abella ,  Jaideep Moses ,  Donald Newell ,  Ravishankar Iyer ,  Ramesh G. Illikkal ,  Srihari Makineni

IPC: G06F9/305 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3009 ,  G06F12/0842

Abstract: Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.

Abstract translation: 描述与基于缓存共享的线程控制相关联的装置和计算系统。 一个实施例包括存储线程控制指令的存储器和执行线程控制指令的处理器。 处理器耦合到存储器。 处理器包括第一单元，用于动态地确定多线程计算系统中的线程之间的高速缓存共享行为，以及第二单元，以动态地控制多线程计算系统中的一组线程的组合。 该组线程的组合至少部分地基于缓存共享行为所表现的线程亲和性。 线程控制指令控制第一单元和第二单元的操作。

公开(公告)号：US20050246500A1

公开(公告)日：2005-11-03

申请号：US10834593

申请日：2004-04-28

Applicant: Ravishankar Iyer ,  Srihari Makineni ,  Ram Huggahalli

Inventor： Ravishankar Iyer ,  Srihari Makineni ,  Ram Huggahalli

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0862

Abstract: In some embodiments, a method, apparatus and system for an application-aware cache push agent. In this regard, a cache push agent is introduced to push contents of memory into a cache of a processor in response to a memory read by the processor of associated contents. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，一种用于应用感知高速缓存推送代理的方法，装置和系统。 在这方面，引入缓存推送代理以响应于由处理器读取相关内容的存储器来将存储器的内容推送到处理器的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US20050114605A1

公开(公告)日：2005-05-26

申请号：US10722884

申请日：2003-11-26

Applicant: Ravishankar Iyer

Inventor： Ravishankar Iyer

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0888

Abstract: Methods and apparatus to process cache allocation requests are disclosed. In an example method, a priority level is assigned to a cache allocation request. Based on the priority level, an allocation probability associated with the cache allocation request is identified. Based on the allocation probability, the cache allocation request is identified with either an allocate condition and a bypass condition.

Abstract translation: 公开了处理高速缓存分配请求的方法和装置。 在示例性方法中，将优先级分配给高速缓存分配请求。 基于优先级，识别与高速缓存分配请求相关联的分配概率。 基于分配概率，使用分配条件和旁路条件来识别高速缓存分配请求。

公开(公告)号：US09378164B2

公开(公告)日：2016-06-28

申请号：US13997651

申请日：2011-12-22

Applicant: Zhen Fang ,  Xiaowei Jiang ,  Srihari Makineni ,  Ramesh G. Illikkal ,  Ravishankar Iyer

Inventor： Zhen Fang ,  Xiaowei Jiang ,  Srihari Makineni ,  Ramesh G. Illikkal ,  Ravishankar Iyer

IPC: G06F13/24 ,  G06F9/32 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/3016 ,  G06F9/327 ,  G06F9/3861 ,  G06F9/4806 ,  G06F9/4812 ,  G06F13/24

Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

Abstract translation: 描述了在半导体芯片上实现的指令流水线。 半导体芯片包括执行单元，以执行中断处理指令。 存储电路用于保存不同组的微操作，其中每组微操作都要处理不同的中断。 第一逻辑电路，用于执行一组所述微操作组，以处理所述集合设计的中断。 第二逻辑电路，用于在所述第一逻辑电路处理所述中断时将程序流返回到调用程序。

公开(公告)号：US09360927B2

公开(公告)日：2016-06-07

申请号：US13992361

申请日：2011-09-06

Applicant: Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadogopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

Inventor： Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadogopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/5094 ,  G06F12/084 ,  G06F13/24 ,  G06F2212/1028 ,  G06F2212/60 ,  G06F2212/62 ,  H04W52/028 ,  H04W88/02 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D70/00

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于从加速器接收中断的方法，响应于该中断将恢复信号直接发送到小型核心，并向第一小型核心提供大型核心的执行状态的子集，以及 确定小型核心是否可以处理与该中断有关的请求，如果该确定是肯定的，则执行与该小核心中的该请求相对应的操作，否则将大的核心执行状态和恢复信号提供给该大核心 。 描述和要求保护其他实施例。

公开(公告)号：US20140314323A1

公开(公告)日：2014-10-23

申请号：US14320092

申请日：2014-06-30

Applicant: Yong Zhang ,  Ravishankar Iyer ,  Rameshkumar G. Illikkal ,  Donald K. Newell ,  Jianping Zhou

Inventor： Yong Zhang ,  Ravishankar Iyer ,  Rameshkumar G. Illikkal ,  Donald K. Newell ,  Jianping Zhou

IPC: G06K9/48 ,  G06K9/00

CPC classification number: G06K9/481 ,  G06K9/00973 ,  G06K9/4671 ,  G06K2009/485

Abstract: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.

Abstract translation: 识别图像的方法和系统可以包括具有硬件模块的装置，该硬件模块具有对于图像中的多个向量的逻辑，基于图像矢量的偶数像素确定第一中间计算，并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。

公开(公告)号：US08858126B2

公开(公告)日：2014-10-14

申请号：US12567129

申请日：2009-09-25

Applicant: Michael Glenn Morrison ,  Srikanth Bontha ,  Juan Seculi ,  Thomas Jerry Long, II ,  Jeremy Joseph Verellen ,  Ravishankar Iyer

Inventor： Michael Glenn Morrison ,  Srikanth Bontha ,  Juan Seculi ,  Thomas Jerry Long, II ,  Jeremy Joseph Verellen ,  Ravishankar Iyer

IPC: B23C5/22 ,  B23C5/20 ,  B23C5/10

CPC classification number: B23C5/1045 ,  B23C5/2221 ,  B23C2200/203 ,  B23C2200/361 ,  B23C2210/168 ,  Y10T407/1908 ,  Y10T407/192 ,  Y10T407/2272 ,  Y10T407/23

Abstract: A cutting tool includes a body having a forward end and a rearward end. The forward end includes an insert-receiving pocket with a threaded hole having a center axis. The cutting tool further includes a cutting insert with a countersunk bore with a center axis. The cutting tool includes an error proofing feature for preventing the cutting insert to be properly mounted in an insert-receiving pocket when an offset distance between the center axis of the threaded hole of the insert-receiving pocket and the center axis of the countersunk bore of the cutting insert is greater than a predetermined percentage of the outer diameter of the threaded screw.

Abstract translation: 切割工具包括具有前端和后端的主体。 前端包括具有中心轴线的螺纹孔的插入物容纳袋。 切削工具还包括具有中心轴的埋头孔的切削刀片。 当刀片接收槽的螺纹孔的中心轴线与埋头孔的中心轴线之间的偏移距离为0°时，切削工具包括防止切削刀片适当地安装在刀片容纳槽中的防错特征 切削刀片大于螺纹螺杆的外径的预定百分比。

公开(公告)号：US20140189299A1

公开(公告)日：2014-07-03

申请号：US13730565

申请日：2012-12-28

Applicant: Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/38

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏一组小型物理处理器核心。

公开(公告)号：US20140092014A1

公开(公告)日：2014-04-03

申请号：US13631309

申请日：2012-09-28

Applicant: Sadagopan Srinivasan ,  Rameshkumar Illikkal ,  Ravishankar Iyer

Inventor： Sadagopan Srinivasan ,  Rameshkumar Illikkal ,  Ravishankar Iyer

IPC: G06F3/033

CPC classification number: G06F3/013 ,  G06F3/017 ,  G06F3/0304

Abstract: Systems and methods may provide for capturing a user input by emulating a touch screen mechanism. In one example, the method may include identifying a point of interest on a front facing display of the device based on gaze information associated with a user of the device, identifying a hand action based on gesture information associated with the user of the device, and initiating a device action with respect to the front facing display based on the point of interest and the hand action.

Abstract translation: 系统和方法可以通过仿真触摸屏机构来提供用于捕获用户输入的功能。 在一个示例中，该方法可以包括基于与设备的用户相关联的凝视信息来识别设备的正面显示器上的兴趣点，基于与设备的用户相关联的手势信息识别手动操作，以及 基于感兴趣的点和手的动作来启动相对于面向前显示器的设备动作。

公开(公告)号：US20140091949A1

公开(公告)日：2014-04-03

申请号：US13993333

申请日：2011-12-30

Applicant: Omesh Tickoo ,  Ravishankar Iyer

Inventor： Omesh Tickoo ,  Ravishankar Iyer

IPC: G08G1/0967

CPC classification number: G08G1/096791 ,  G01C21/3492 ,  G08G1/0965 ,  G08G1/161 ,  H04W4/024 ,  H04W4/027 ,  H04W4/46 ,  H04W84/18

Abstract: An ad hoc network may be established between vehicles using a wireless connection. The wireless network may be used for sending and receiving information about road conditions, such as average speed, a location and configuration of a road obstruction, images of an accident scene, and a traffic flow plan. The wireless network may also be used for communicating with emergency response vehicles in order to enable faster and more effective responses to accidents.

Abstract translation: 可以使用无线连接在车辆之间建立自组织网络。 无线网络可以用于发送和接收关于道路状况的信息，例如平均速度，道路障碍物的位置和配置，事故场景的图像和交通流量计划。 无线网络还可以用于与紧急响应车辆进行通信，以便能够更快且更有效地应对事故。