公开(公告)号：US20040152335A1

公开(公告)日：2004-08-05

申请号：US10612068

申请日：2003-07-03

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Koji Ida

IPC: H01L021/31

CPC classification number: H01L21/76224 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3144 ,  H01L21/3185

Abstract: A silicon nitride film and a silicon oxynitride film as an antireflection coating are successively formed on a silicon substrate. The silicon nitride film and the silicon oxynitride film are patterned. A reduction treatment for reducing the amount of oxygen atoms is performed on the silicon oxynitride film. The silicon oxynitride film after the reduction treatment and the silicon nitride film are used as a mask to etch the silicon substrate, thereby forming a trench in a main surface of the silicon substrate. This trench is filled with an insulating film.

公开(公告)号：US20040151992A1

公开(公告)日：2004-08-05

申请号：US10714362

申请日：2003-11-17

Applicant: RENESAS TECHNOLOGY CORP. ,  TOPPAN PRINTING CO., LTD

Inventor： Yoshikazu Nagamura ,  Kouji Tange ,  Kouki Hayashi ,  Hidehiro Ikeda

IPC: G03F009/00

CPC classification number: G03F1/74 ,  G03F1/32

Abstract: A shading area having a transmissivity in the range of 0 to 2% is formed at the center of a clear defect in a wiring pattern of a halt tone mask. Semitransparent areas having a transmissivity in the range of 10 to 25% are formed, adjacently to shading area, in areas extending from the inside of the edge of an imaginary pattern having no defect to the outside of the edge. In this way, in the correction of the defect in the half tone mask, the working accuracy tolerable margin of the correction portion of the defect can be made large.

Abstract translation: 在停止色调掩模的布线图案的清晰缺陷的中心处形成具有在0至2％范围内的透射率的阴影区域。 在从没有缺陷的假想图案的边缘的内部延伸到边缘的外侧的区域中，形成具有在10至25％范围内的透射率的半透明区域，与阴影区域相邻。 以这种方式，在校正半色调掩模中的缺陷时，可以使缺陷的校正部分的加工精度可容许余量变大。

公开(公告)号：US20040147137A1

公开(公告)日：2004-07-29

申请号：US10695798

申请日：2003-10-30

Applicant: Renesas Technology Corp.

Inventor： Atsushi Hiraiwa ,  Satoshi Sakai ,  Dai Ishikawa ,  Yoshihiro Ikeda

IPC: H01L021/31

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/3105 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.

Abstract translation: 根据本发明，可以通过低温处理形成膜质量几乎等于热氧化物的氧化膜。 在构成半导体晶片的基板的有源区域上去除绝缘体之后，通过低压CVD法在半导体晶片的主表面上沉积由例如氧化硅制成的绝缘体。 该绝缘体是在后续步骤中形成MISFET的栅极绝缘体的膜。 随后，按照箭头示意性地示出的方式，在含有氧的气氛（氧等离子体处理）中对绝缘体进行等离子体处理。 通过这样做，通过CVD方法形成的绝缘体的膜质量可以提高到与由热氧化物形成的绝缘体几乎相同的程度。

公开(公告)号：US20040144488A1

公开(公告)日：2004-07-29

申请号：US10632953

申请日：2003-08-04

Applicant: Renesas Technology Corp.

Inventor： Takayuki Shoya ,  Masaru Nagano

IPC: H01L021/306

CPC classification number: G03F7/70866 ,  G03F7/70875

Abstract: A photolithography apparatus includes: an air supply line supplying an air to a chamber processing a wafer; a temperature and humidity adjuster provided to the air supply line; a temperature and humidity monitoring sensor sensing temperature and humidity internal to the chamber; and a controller connected to the temperature and humidity monitoring sensor and the temperature and humidity adjuster to control the temperature and humidity adjuster to supply the chamber via the air supply line with an air having the same temperature and humidity as those of the air in the chamber detected by the temperature and humidity monitoring sensor.

Abstract translation: 光刻设备包括：向处理晶片的腔室供应空气的空气供应管线; 提供给供气管线的温度和湿度调节器; 温度和湿度监测传感器感测室内部的温度和湿度; 以及连接到温度和湿度监测传感器和温度和湿度调节器的控制器，以控制温度和湿度调节器，以通过空气供应管线提供具有与室内空气相同的温度和湿度的空气 由温湿度监测传感器检测。

公开(公告)号：US20040140552A1

公开(公告)日：2004-07-22

申请号：US10737119

申请日：2003-12-17

Applicant: Renesas Technology Corp.

Inventor： Hiroshi Kuroda ,  Nobuhiro Kinoshita

IPC: H01L023/053

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83

Abstract: There is provided a small and high-performance System in Package (SiP) suitable for high-density mounting. A System in Package (SiP) has a stack structure such that two memory chips are stacked and mounted over the main surface of a wiring substrate, a microcomputer chip is stacked and mounted over the upper part thereof, and the chips are sealed by a mold resin. Each of the memory chips is constructed so as to transmit and receive data to/from the outside of the system via the microcomputer chip. The microcomputer chip is constructed of a multiport structure having various interfaces between it and the outside of the system in addition to an interface between it and the inside of the system. The number of terminals (pins) of the microcomputer chip is much larger than that of the memory chips.

Abstract translation: 提供了适用于高密度安装的小型和高性能系统级封装（SiP）。 包装系统（SiP）具有堆叠结构，使得两个存储芯片堆叠并安装在布线基板的主表面上，微计算机芯片堆叠并安装在其上部，并且芯片被模具密封 树脂。 每个存储器芯片被构造成经由微计算机芯片向/从系统的外部发送和接收数据。 除了其与系统内部的接口之外，微型计算机芯片由具有与系统外部各种接口的多端口结构构成。 微型计算机芯片的端子（引脚）数量远大于存储器芯片的数量。

公开(公告)号：US20040140467A1

公开(公告)日：2004-07-22

申请号：US10612066

申请日：2003-07-03

Applicant: RENESAS TECHNOLOGY CORP. ,  KYOEI SANGYO CO., LTD.

Inventor： Naoki Kimura ,  Keiji Sugihara

IPC: H01L023/58

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05673 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/05042 ,  H01L2924/19043 ,  H01L2924/00014

Abstract: In a semiconductor device having a pad, a first conductor and a second conductor are arranged at a surface of the pad. The first conductor has hardness that is greater than that of the second conductor and not less than that of a probe stylus. The first conductor is arranged at the surface of the pad such that the probe stylus hits or rubs against the first conductor at least one time while the probe stylus is in contact with and sliding on the surface of the pad.

公开(公告)号：US20040137853A1

公开(公告)日：2004-07-15

申请号：US10742813

申请日：2003-12-23

Applicant: Renesas Technology Corp. ,  TTPCom Limited

Inventor： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC: H04B007/00

CPC classification number: H04B1/30 ,  H03D2200/0047 ,  H03K21/16

Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Abstract translation: 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。

公开(公告)号：US20040137649A1

公开(公告)日：2004-07-15

申请号：US10437911

申请日：2003-05-15

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takeshi Kishida ,  Shigenori Kido

IPC: H01L021/00

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A photolithography step is carried out for exposing/etching a resist film in an etching step. Thereafter a superposition inspection step employing a superposed layer superposition mark and a resist film superposition mark is carried out with a superposition inspection apparatus. In this step, an applied mask confirmation step is simultaneously carried out with the superposition inspection apparatus. Thus, it is possible to provide a method of fabricating a semiconductor device including a superposition inspection step, capable of efficiently confirming an applied mask and improving the fabrication yield for the semiconductor device.

Abstract translation: 在蚀刻步骤中进行曝光/蚀刻抗蚀剂膜的光刻步骤。 此后，使用重叠检查装置进行使用叠加层叠加标记和抗蚀剂膜叠加标记的叠加检查步骤。 在该步骤中，与叠加检查装置同时进行应用的掩模确认步骤。 因此，可以提供一种制造包括叠加检查步骤的半导体器件的方法，其能够有效地确认所施加的掩模并且提高半导体器件的制造成品率。

公开(公告)号：US20040124506A1

公开(公告)日：2004-07-01

申请号：US10729950

申请日：2003-12-09

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd. ,  Renesas Eastern Japan Semiconductor, Inc.

Inventor： Fujio Ito ,  Hiromichi Suzuki ,  Hiroyuki Takeno ,  Hiroshi Shimoji ,  Fumio Murakami ,  Keiko Kurakawa

IPC: H01L023/495

CPC classification number: H01L24/97 ,  H01L21/565 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract translation: 旨在提高QFN（四方扁平无铅封装）的生产成本，达到多引脚结构。 在通过模塑形成用于密封半导体芯片的树脂密封构件之后，树脂密封构件的周边部分和引线框架都沿着位于树脂密封构件的内侧（树脂密封构件的中心侧）上的切割线切割 沿着树脂密封构件的外缘延伸的线（成型线），从而覆盖暴露于树脂密封构件的侧面（切割面）的各个引线的整个表面（上下表面和两个侧面） 树脂，从而防止在引线的切割面上发生金属毛刺。

公开(公告)号：US20040120195A1

公开(公告)日：2004-06-24

申请号：US10725477

申请日：2003-12-03

Applicant: Renesas Technology Corp.

Inventor： Yuichi Okuda

IPC: G11C029/00

CPC classification number: H01L23/576 ,  G06K19/073 ,  G06K19/07372 ,  G11C11/412 ,  G11C11/4125 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously. Reverse engineering by irradiation with light can be effectively prevented.

Abstract translation: 提供一种能够防止卡黑入侵的半导体集成电路，由此通过照射光和被保护的秘密信息主动地引起错误的动作被非法获取。 由标准逻辑处理配置的光检测器安装在诸如IC卡微计算机的半导体集成电路上，与其他电路几乎不区分并且消耗非常少的待机功率。 例如，每个光电检测器具有这样的配置，其中第一状态通过其初始化动作保持在静态锁存器中，并且当非导通状态的半导体元件构成静态锁存器时，发生反向到第二状态 第一个状态被光照射。 多个光电检测器被布置在存储单元阵列中。 通过将静态锁存型光电检测器结合到存储器阵列中，它们可以不显眼地排列。 可以有效地防止用光照射进行逆向工程。