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公开(公告)号：US11699660B2
公开(公告)日：2023-07-11
申请号：US17180094
申请日：2021-02-19
Applicant: SOCIONEXT INC.
Inventor： Isaya Sobue , Hidetoshi Tanaka , Mai Tsukamoto
IPC: H01L23/528 , H01L27/02
CPC classification number: H01L23/5286 , H01L27/0292
Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.
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公开(公告)号：US20230216518A1
公开(公告)日：2023-07-06
申请号：US18182128
申请日：2023-03-10
Applicant: Socionext Inc.
Inventor： Itsuki YOSHIDA , Takashi MORIE
Abstract: A comparator circuit outputs first and second digital signals corresponding to differential signals to a flip-flop having a predetermined forbidden input combination. A converter circuit performs differential amplification for the differential signals and converts the resultant signals to first and second signals that are complementary digital signals. A logic circuit performs predetermined logical operation, and when the logical values of the first and second signals are different from each other, outputs the first and second digital signals corresponding to the logical values of the first and second signals, and when the logical values of the first and second signals are the same, outputs the first and second digital signals having a same value other than the predetermined forbidden input combination.
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公开(公告)号：US11652459B2
公开(公告)日：2023-05-16
申请号：US17716792
申请日：2022-04-08
Applicant: SOCIONEXT INC.
Inventor： Armin Jalili Sebardan , Alistair John Gratrex
CPC classification number: H03F3/45264 , H03F1/3205 , H03F1/3211 , H03F2203/45296 , H03F2203/45298 , H03F2203/45318 , H03F2203/45326
Abstract: Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.
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公开(公告)号：US11621259B2
公开(公告)日：2023-04-04
申请号：US17233177
申请日：2021-04-16
Applicant: SOCIONEXT INC.
Inventor： Toshihiro Nakamura , Taro Fukunaga
IPC: H01L27/02 , H01L23/528 , H01L23/00
Abstract: A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.
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公开(公告)号：US20230046171A1
公开(公告)日：2023-02-16
申请号：US17864966
申请日：2022-07-14
Applicant: Socionext Inc.
Inventor： Kenneth Stephen HUNT , Antoine MORINEAU , Aadilhussain MANIYAR
Abstract: A comparator including: first and second input transistors connected to control signals at first and second nodes of the comparator; latch circuitry; at least one controllable offset-correction component having an input terminal and connected to control the signal at one of the first and second nodes based on an offset-correction signal provided at its input terminal; for each controllable offset-correction component, an offset correction circuit configured to provide the offset-correction signal provided at its input terminal; and control circuitry. The control circuitry controls the at least one offset-correction circuit to: control an amount by which the offset-correction signal is adjusted; and/or in a bypass operation, connect the input terminal of the at least one controllable offset-correction component to a bypass-operation reference voltage supply; and/or in a maintenance operation, control the charging-operation voltage supply and/or the bypass-operation voltage supply to control leakage of the charge stored on the holding capacitor.
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Patent Agency Ranking
公开(公告)号：US20230042275A1
公开(公告)日：2023-02-09
申请号：US17966396
申请日：2022-10-14
Applicant: Socionext Inc.
Inventor： Yukihiro SASAGAWA
Abstract: A network quantization method is a network quantization method of quantizing a neural network, and includes a database construction step of constructing a statistical information database on tensors that are handled by neural network, a parameter generation step of generating quantized parameter sets by quantizing values included in each tensor in accordance with the statistical information database and the neural network, and a network construction step of constructing a quantized network by quantizing the neural network with use of the quantized parameter sets. The parameter generation step includes a quantization-type determination step of determining a quantization type for each of a plurality of layers that make up the neural network.
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公开(公告)号：US11574751B2
公开(公告)日：2023-02-07
申请号：US16721193
申请日：2019-12-19
Applicant: SOCIONEXT INC.
Inventor： Dierk Tiedemann , Niklas Linkewitsch
Abstract: A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X
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公开(公告)号：US20230036535A1
公开(公告)日：2023-02-02
申请号：US17850202
申请日：2022-06-27
Applicant: Socionext Inc.
Inventor： Saul DARZY , Ozcan TUNCTURK
IPC: H03K17/687 , H03M1/12 , H03M1/66
Abstract: A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.
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公开(公告)号：US20230034555A1
公开(公告)日：2023-02-02
申请号：US17859658
申请日：2022-07-07
Applicant: Socionext Inc.
Inventor： Jayaraman KUMAR , Kenneth Stephen HUNT
Abstract: Mixed-signal circuitry including a set of capacitive digital-to-analogue converter, CDAC, units for carrying out digital-to-analogue conversion operations to convert respective digital values into corresponding analogue values; and control circuitry, where: each CDAC unit includes an array of capacitors at least some of which are configured to be individually-switched dependent on the digital values, the capacitors configured to have nominal capacitances; a given capacitor of the array of capacitors in each of the CDAC units is a target capacitor; the set of CDAC units includes a plurality of sub-sets of CDAC units; at least one of the target capacitors per sub-set of CDAC units is a variable capacitor, controllable by the control circuitry to have any one of a plurality of nominal capacitances defined by the configuration of that capacitor.
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公开(公告)号：US11563985B2
公开(公告)日：2023-01-24
申请号：US16257317
申请日：2019-01-25
Applicant: Socionext Inc.
Inventor： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
IPC: G06F9/38 , H04N19/86 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/436 , H04N19/523
Abstract: A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.
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