公开(公告)号：US6080661A

公开(公告)日：2000-06-27

申请号：US87441

申请日：1998-05-29

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76897

Abstract: Disclosed are methods for making reliable conductive vias in semiconductor devices that are fabricated over a semiconductor wafer. The semiconductor device includes a plurality of transistor devices having diffusion regions and polysilicon gate electrodes, and an oxide material that covers a top surface of the polysilicon gate electrodes of the transistor devices. A silicon nitride layer is also disposed over the semiconductor devices and a dielectric layer is disposed over the silicon nitride layer. The method includes depositing a silicon nitride layer over the dielectric layer, and etching nitride windows in the silicon nitride layer to expose the dielectric layer where conductive contacts to selected polysilicon gate electrodes are desired. The method then includes pattering a photoresist mask over the silicon nitride layer. The photoresist mask is configured to have a plurality of windows defining all contacts to both selected ones of the diffusion regions and selected ones of the polysilicon gate electrodes, and some of the plurality of windows are defined over the nitride windows. Furthermore, the method includes performing a series of dielectric and silicon nitride etch operations to substantially simultaneously form via holes down to selected polysilicon gate electrodes and selected diffusion regions. Once the via holes are etched, a suitable conductive contact fill process may be performed.

Abstract translation: 公开了在半导体晶片上制造的半导体器件中制造可靠的导电通孔的方法。 半导体器件包括具有扩散区域和多晶硅栅电极的多个晶体管器件和覆盖晶体管器件的多晶硅栅电极的顶表面的氧化物材料。 氮化硅层也设置在半导体器件上方，并且介电层设置在氮化硅层上。 该方法包括在电介质层上沉积氮化硅层，以及蚀刻氮化硅层中的氮化物窗口以暴露需要与所选择的多晶硅栅电极的导电接触的电介质层。 该方法然后包括在氮化硅层上图案化光致抗蚀剂掩模。 光致抗蚀剂掩模被配置为具有多个窗口，其限定了所选择的扩散区域中的所选择的一个以及多晶硅栅极电极中的所选择的多个栅电极的所有触点，并且多个窗口中的一些限定在氮化物窗口上。 此外，该方法包括执行一系列电介质和氮化硅蚀刻操作，以基本上同时形成向下选定的多晶硅栅电极和选定扩散区的通孔。 一旦通孔被蚀刻，就可以执行合适的导电接触填充过程。

公开(公告)号：US6034434A

公开(公告)日：2000-03-07

申请号：US024967

申请日：1998-02-06

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L23/52

CPC classification number: H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/522 ,  H01L2924/0002

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract translation: 公开了一种在化学机械研磨过程中用于调节抛光垫的目的，在半导体晶片的表面上形成尖锐的氧化物峰的方法。 为了在晶片的表面上产生氧化物峰，将另外的元素添加到晶片的迹线层。 使用电子回旋加速器共振化学气相沉积工艺在附加元件上沉积氧化物层，其包括溅射步骤，以便在附加管线上的氧化物层中产生尖锐的峰。 在一些实施例中，附加元件可以由多个矩形块形成，在其上形成金字塔状氧化物峰。 在另一些实施例中，它们可以由多个矩形块形成，该矩形块通过分别形成有金字塔形氧化物峰和刀刃峰的窄线连接。

公开(公告)号：US5985749A

公开(公告)日：1999-11-16

申请号：US881614

申请日：1997-06-25

Applicant: Xi-Wei Lin ,  Subhas Bothra

Inventor： Xi-Wei Lin ,  Subhas Bothra

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76843

Abstract: The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.

Abstract translation: 本发明涉及集成电路和包括硅化钨阻挡层的通孔结构以及形成这种通孔结构的方法。 在一个示例性实施例中，在通孔的侧壁和底表面上形成金属层，通过化学气相沉积在第一金属层上形成WSix阻挡层，随后填充金属孔。 硅化钨阻挡层有效地抑制了在插塞形成期间从气孔物质从通孔的侧壁释放出来的装置劣化。 因此可以制造半导体器件，其由于不完全的通孔填充而免疫或不易受金属开路故障的影响。

公开(公告)号：US5889389A

公开(公告)日：1999-03-30

申请号：US14832

申请日：1998-01-28

Applicant: Subhas Bothra ,  Jayarama N. Shenoy

Inventor： Subhas Bothra ,  Jayarama N. Shenoy

IPC: H01G5/013 ,  H01M10/46

CPC classification number: H01G5/0138

Abstract: The present invention is a micro-electromechanical voltage shifter. According to one embodiment, the voltage shifter of the present invention comprises a capacitor and micro-electromechanical means for changing a capacitance of the capacitor. The capacitor is initially charged and then electrically isolated. When the capacitance is altered, potential difference across the capacitor is shifted accordingly. In one embodiment of the present invention, the micro-electromechanical means includes a gear wheel driven by a micro-motor. The gear wheel preferably includes a plurality of teeth protruding along a circumference of the gear wheel. Further, the gear wheel is positioned next to the capacitor and configured to move the teeth into and out of a gap between the capacitor plates. As the teeth is preferably made of dielectric material, the voltage across the capacitor is changed as a tooth enters or leaves the gap. In another embodiment, the teeth may be made of a conducting material. The thickness of the teeth may also vary to provide a wide range of voltage levels.

Abstract translation: 本发明是一种微机电电压转换器。 根据一个实施例，本发明的电压转换器包括用于改变电容器的电容的电容器和微机电装置。 电容器最初被充电然后被电隔离。 当电容变化时，电容器两端的电位差相应地移动。 在本发明的一个实施例中，微机电装置包括由微型电动机驱动的齿轮。 齿轮优选地包括沿着齿轮的圆周突出的多个齿。 此外，齿轮位于电容器旁边并且被配置成将齿移入和移出电容器板之间的间隙。 由于齿优选由介电材料制成，所以当齿进入或离开间隙时，电容器两端的电压发生变化。 在另一个实施例中，齿可以由导电材料制成。 齿的厚度也可以改变以提供宽范围的电压水平。

公开(公告)号：US5854510A

公开(公告)日：1998-12-29

申请号：US883403

申请日：1997-06-26

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC: H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract translation: 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5639697A

公开(公告)日：1997-06-17

申请号：US593900

申请日：1996-01-30

Applicant: Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

Inventor： Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

IPC: H01L21/3105 ,  H01L21/302 ,  H01L21/463

CPC classification number: H01L21/31053 ,  Y10S438/926

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract translation: 公开了用于不同层的半导体晶片的形貌图案密度的方法，以改进在晶片处理期间使用的化学机械抛光工艺。 为了实现晶片表面上的预定图案形状密度，根据需要将虚拟凸起线插入到迹线层上的有源导电迹线之间的间隙中。 在一些实施例中，预定图案密度在大约40％至80％的范围内。 在一些应用中，活性导电迹线和虚拟凸起线都由金属材料形成，该金属材料在化学机械抛光过程之前在一个步骤中沉积，绝缘层沉积在两个有源导电迹线和虚拟凸起线上 。 在其他应用中，假凸起线由绝缘层形成。

公开(公告)号：US20070083833A1

公开(公告)日：2007-04-12

申请号：US11244514

申请日：2005-10-06

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

Abstract translation: 本发明的实施例提供了一种系统和方法，用于在设计期间使用诸如位置和路线工具或布局工具的工具来实现金属填充。 与在设计和布局之后执行金属填充的现有已知解决方案不同，在布局期间，根据要制造的器件的设计规则，均匀地形成导电迹线图案并进行间隔，从而实现更多的规划和设计，进行金属填充。 在设计和布局期间，将导电迹线划分为有源和无源段可以在设计和布局期间识别器件内的关键或敏感器件元件的潜在负面影响。 以前，设计和布局后实施了金属填充，并且经常导致IC设计中以前未考虑的负面影响。 本发明的实施例减少了在设计和布局之后掺入金属填充物的其他装置中的劣化。 另外，因为在IC的设计和布局期间考虑了非活性金属填充段的物理特性。

公开(公告)号：US06717232B2

公开(公告)日：2004-04-06

申请号：US10406914

申请日：2003-04-02

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L2900

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/042 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor inductor and a method for making a semiconductor inductor are provided. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench within the oxide layer. The oxide layer is also etched to form a first inductor trench within the oxide layer such that the first inductor trench is defined in an inductor geometry. The oxide layer is then etched to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry. After the oxide layer is etched, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with copper. The semiconductor inductor is configured to have a low resistance and a high quality factor.

Abstract translation: 提供半导体电感器和制造半导体电感器的方法。 蚀刻设置在衬底上的氧化物层以在氧化物层内形成互连金属化沟槽。 也蚀刻氧化物层以在氧化物层内形成第一电感器沟槽，使得第一电感器沟槽以电感器几何形状限定。 然后蚀刻氧化物层以在互连金属化沟槽中形成至少一个通孔，以及在氧化物层中的第一电感器沟槽上方的第二电感器沟槽。 第二电感沟槽也具有电感器几何形状。 在蚀刻氧化物层之后，铜填充至少一个通孔，第二电感器沟槽，互连金属化沟槽和第一电感器沟槽。 半导体电感器被配置为具有低电阻和高品质因数。

公开(公告)号：US06649253B1

公开(公告)日：2003-11-18

申请号：US09523403

申请日：2000-03-10

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L2500

CPC classification number: B24B37/013 ,  B24B37/042 ,  H01L21/31053 ,  Y10S438/959 ,  Y10T428/24917

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

Abstract translation: 使用具有优化的光学性质的膜用于化学机械抛光（CMP）端点检测的方法。 具体地，本发明的一个实施方案包括用于改进化学机械抛光终点检测的方法。 该方法包括在反射停止层上沉积介电层的步骤。 反射阻挡层设置在配置在半导体晶片上的部件的上方。 在使用光的反射信号确定介电层的厚度期间，反射率停止层基本上减少了从组件反射的任何光。 因此，本发明提供了一种在半导体晶片的CMP工艺期间提供更准确的端点检测的方法和系统。 作为本发明的结果，CMP机器的操作者精确地知道何时停止半导体晶片的CMP工艺。 此外，本发明使得CMP机器的操作者能够在半导体晶片的CMP处理之后以一定的精度了解剩余的膜（例如介电层）的厚度。 此外，本发明基本上消除了半导体晶片的过度的化学机械抛光。 因此，为了补偿半导体晶片的过度的化学机械抛光，不需要在晶片上沉积太多的介电材料。 因此，本发明能够降低半导体晶片的制造成本。

公开(公告)号：US06569757B1

公开(公告)日：2003-05-27

申请号：US09429540

申请日：1999-10-28

Applicant: Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

Inventor： Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

IPC: H01L214763

CPC classification number: H01L23/5225 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  Y10T29/49123 ,  H01L2924/00

Abstract: A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Abstract translation: 提供了在电介质层中形成同轴互连线的方法。 该方法包括在电介质层中限定沟槽，然后在沟槽内形成屏蔽金属化层。 在形成屏蔽金属化层之后，在屏蔽金属化层内沉积保形氧化物层。 然后在保形氧化物层内形成中心导体。 一旦形成中心导体，就在中心导体上沉积填充氧化物层。 然后在填充氧化物层上形成帽金属化层，并与屏蔽金属化层接触。