公开(公告)号：US20110272739A1

公开(公告)日：2011-11-10

申请号：US12775006

申请日：2010-05-06

Applicant: Tsung-Lin LEE ,  Chih-Hao CHANG ,  Chih-Hsin KO ,  Feng YUAN ,  Jeff J. XU

Inventor： Tsung-Lin LEE ,  Chih-Hao CHANG ,  Chih-Hsin KO ,  Feng YUAN ,  Jeff J. XU

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract translation: 一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。 该凹腔具有下部和上部。 下部具有第一应变层和第一介电膜。 第一应变层设置在隔离结构和第一介电膜之间。 第一电介质膜的厚度小于第一应变层的厚度。 上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

公开(公告)号：US20110133292A1

公开(公告)日：2011-06-09

申请号：US12843595

申请日：2010-07-26

Applicant: Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC: H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/76 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract translation: 集成电路结构包括半导体衬底和半导体衬底上的FinFET。 FinFET包括半导体鳍片; 顶表面上的栅极电介质和半导体鳍片的侧壁; 栅电极上的栅电极; 以及在半导体鳍片的端部处的源极/漏极区域。 第一对浅沟槽隔离（STI）区域包括直接在源极/漏极区域的下方部分的部分，其中第一对STI区域被分隔开并邻接半导体条带。 第一对STI区域还具有第一顶面。 第二对STI区域包括直接位于栅极电极下方的部分，其中第二对STI区域彼此分离并邻接半导体条带。 第二对STI区域具有高于第一顶表面的第二顶表面。

公开(公告)号：US20110097889A1

公开(公告)日：2011-04-28

申请号：US12843693

申请日：2010-07-26

Applicant: Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

Inventor： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC: H01L21/28

CPC classification number: H01L21/845 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract translation: 形成集成电路结构的方法包括提供包括顶表面的半导体衬底; 在所述半导体衬底中形成第一绝缘区域和第二绝缘区域; 并使第一绝缘区域和第二绝缘区域凹陷。 第一绝缘区域和第二绝缘区域的剩余部分的顶表面是平坦表面或表面。 第一绝缘区域和第二绝缘区域的相邻去除部分之间的半导体衬底的一部分形成翅片。

公开(公告)号：US07714376B2

公开(公告)日：2010-05-11

申请号：US11612500

申请日：2006-12-19

Applicant: Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L21/28273

Abstract: Non-volatile memory device with polysilicon spacer and method of forming the same. A dielectric layer lines a sidewall of a polysilicon gate. A polysilicon spacer is patterned on the dielectric layer adjacent to the sidewall of the polysilicon gate. A protection spacer is patterned on the dielectric layer and disposed on the polysilicon spacer adjacent to the sidewall of the conductive gate for preventing a shortage path between the polysilicon gate and the polysilicon spacer during a subsequent silicidation process.

Abstract translation: 具有多晶硅间隔物的非挥发性存储器件及其形成方法。 电介质层对多晶硅栅极的侧壁进行配线。 在与多晶硅栅极的侧壁相邻的电介质层上构图多晶硅间隔物。 保护间隔物在电介质层上图案化，并且设置在与导电栅极的侧壁相邻的多晶硅间隔物上，以防止在随后的硅化过程期间多晶硅栅极和多晶硅间隔物之间​​的短路径。

公开(公告)号：US07511988B2

公开(公告)日：2009-03-31

申请号：US11483819

申请日：2006-07-10

Applicant: Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

Inventor： Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

IPC: G11C11/41 ,  G11C7/02 ,  G11C7/24

CPC classification number: G11C11/4125

Abstract: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.

Abstract translation: 静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。 开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。

公开(公告)号：US20080142867A1

公开(公告)日：2008-06-19

申请号：US11612500

申请日：2006-12-19

Applicant: Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7887 ,  H01L21/28273

Abstract: Non-volatile memory device with polysilicon spacer and method of forming the same. A dielectric layer lines a sidewall of a polysilicon gate. A polysilicon spacer is patterned on the dielectric layer adjacent to the sidewall of the polysilicon gate. A protection spacer is patterned on the dielectric layer and disposed on the polysilicon spacer adjacent to the sidewall of the conductive gate for preventing a shortage path between the polysilicon gate and the polysilicon spacer during a subsequent silicidation process.

Abstract translation: 具有多晶硅间隔物的非易失性存储器件及其形成方法。 电介质层对多晶硅栅极的侧壁进行配线。 在与多晶硅栅极的侧壁相邻的电介质层上构图多晶硅间隔物。 保护间隔物在电介质层上图案化，并且设置在与导电栅极的侧壁相邻的多晶硅间隔物上，以防止在随后的硅化过程期间多晶硅栅极和多晶硅间隔物之间​​的短路径。

公开(公告)号：US07355236B2

公开(公告)日：2008-04-08

申请号：US11313790

申请日：2005-12-22

Applicant: Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L29/76

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/7881

Abstract: Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second region of the second conductivity type is formed in the semiconductor substrate spaced apart from the first region. A channel region connects the first and second regions for the conduction of charges. A dielectric layer is disposed on the channel region. A control gate is disposed on the dielectric layer. A tunnel dielectric layer is conformably formed on the semiconductor substrate and the control gate. Two charge storage dots are spaced apart from each other at opposing lateral edges of the sidewalls of the control gate and surface of the semiconductor substrate.

Abstract translation: 具有多晶硅存储点的非易失性浮动栅极存储单元及其制造方法。 非易失性浮动栅极存储单元包括第一导电类型的半导体衬底。 在半导体衬底中形成不同于第一导电类型的第二导电类型的第一区域。 第二导电类型的第二区域形成在与第一区域间隔开的半导体衬底中。 通道区域连接第一和第二区域用于电荷传导。 电介质层设置在沟道区上。 控制栅极设置在电介质层上。 在半导体衬底和控制栅上一致地形成隧道介电层。 两个电荷存储点在控制栅极的侧壁和半导体衬底的表面的相对侧边缘处彼此间隔开。

公开(公告)号：US20070238237A1

公开(公告)日：2007-10-11

申请号：US11402529

申请日：2006-04-11

Applicant: Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

Inventor： Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.

Abstract translation: 非易失性半导体存储器件包括形成在衬底，半导体间隔物，氧化物 - 氮化物 - 氧化物堆叠和接触焊盘上的栅堆叠。 半导体间隔物邻近栅极堆叠的两侧并在衬底上方。 氧化物 - 氧化物 - 氧化物堆叠位于间隔物和栅极堆叠之间，并且位于间隔物和衬底之间，使得氧化物 - 氧化物 - 氧化物堆叠在至少一侧上具有大致L形的横截面 门堆叠。 接触垫在栅极电极和半导体间隔物之间​​是电接触的。 接触焊盘可以进一步形成在栅电极和半导体间隔物之间​​的氧化物 - 氮化物 - 氧化物堆叠的凹陷部分。 接触焊盘可以包括其上形成有金属硅化物的外延硅。

公开(公告)号：US20070212841A1

公开(公告)日：2007-09-13

申请号：US11602809

申请日：2006-11-21

Applicant: Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28282 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.

Abstract translation: 栅极堆叠形成在基板上。 栅极堆叠具有侧壁。 氧化物 - 氮化物 - 氧化物材料沉积在栅极叠层上。 除去氧化物 - 氮化物 - 氧化物材料的一部分以形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构具有通常为L形的横截面，沿着栅极叠层侧壁的至少一部分和沿着衬底的水平部分具有垂直部分。 顶部氧化物材料沉积在衬底上。 在顶部氧化物材料上沉积氮化硅间隔物材料。 除去顶部氧化物材料和氮化硅间隔物材料的部分以形成通过顶部氧化物材料从氧化物 - 氮化物 - 氧化物堆叠体分离的氮化硅间隔物。 源极/漏极区域形成在衬底中。

公开(公告)号：US06868130B2

公开(公告)日：2005-03-15

申请号：US09840987

申请日：2001-04-25

Applicant: Tsung-Lin Lee

Inventor： Tsung-Lin Lee

IPC: H04L25/06 ,  H04L27/26 ,  H04L27/16

CPC classification number: H04L25/069 ,  H04L27/2647

Abstract: A transmission mode detector for digital receiver is proposed. The transmission mode detector comprises a RF tuner for receiving RF signals and generating intermediate frequency (IF) signals. An envelope detector is employed to filter the IF signals and generate rough envelope signal and a hard-decision machine is employed to quantize the rough envelope signal into hard-decision binary signals. The transmission mode detector further comprises a glitch remover to remove the unwanted glitch in the binary signals and generate envelope signal. An A/D converter is used to quantize the IF signals and generate digital signal. Further more, an I/Q de-multiplexer is used to extract the in-phase and the quadrature terms of the OFDM symbol from the digital signal. The transmission mode detector then detects the transmission mode by a mode detect unit according to the period of the envelope signal. If the detected mode is mode II or III, then the mode detect unit further distinguishes the transmission mode based on the auto-correlations of the OFDM symbol.

Abstract translation: 提出了一种数字接收机的传输模式检测器。 传输模式检测器包括用于接收RF信号并产生中频（IF）信号的RF调谐器。 采用包络检波器对IF信号进行滤波并产生粗糙包络信号，采用硬判决机将粗糙包络信号量化为硬决策二进制信号。 传输模式检测器还包括毛刺去除器以去除二进制信号中的不需要的毛刺并产生包络信号。 A / D转换器用于量化IF信号并产生数字信号。 此外，使用I / Q解复用器从数字信号中提取OFDM符号的同相和正交项。 传输模式检测器然后根据包络信号的周期通过模式检测单元检测传输模式。 如果检测模式是模式II或III，则模式检测单元进一步基于OFDM符号的自相关来区分传输模式。