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    READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
    51.
    发明申请
    READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA 有权
    DDR3应用于FPGA的阅读实施

    公开(公告)号：US20090296503A1

    公开(公告)日：2009-12-03

    申请号：US12539582

    申请日：2009-08-11

    申请人： Michael H.M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

    发明人： Michael H.M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

    摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

    摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

    PVT compensated auto-calibration scheme for DDR3
    52.
    发明授权
    PVT compensated auto-calibration scheme for DDR3 有权
    用于DDR3的PVT补偿自动校准方案

    公开(公告)号：US07590008B1

    公开(公告)日：2009-09-15

    申请号：US11936036

    申请日：2007-11-06

    申请人： Manoj B. Roge ,  Andrew Bellis ,  Philip Clarke ,  Joseph Huang ,  Michael H. M. Chu ,  Yan Chong

    发明人： Manoj B. Roge ,  Andrew Bellis ,  Philip Clarke ,  Joseph Huang ,  Michael H. M. Chu ,  Yan Chong

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C5/04 ,  G11C7/04 ,  G11C7/10 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    摘要： Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

    摘要翻译： 提供高速存储器接口的输入和输出电路校准的电路，方法和设备。 由存储器接口提供的时钟信号的飞越路由引起的定时错误针对读取和写入路径进行校准。 这包括调整每个DQ / DQS组的读和写DQS信号定时，以及当定时误差大于一个时钟周期时插入或旁路寄存器。 由CK，DQ和DQS信号之间的跟踪和驱动器不匹配引起的定时偏移被补偿。 这些校准中的一个或多个可以在设备操作期间通过跟踪例程更新。

    Read-side calibration for data interface
    53.
    发明授权
    Read-side calibration for data interface 有权
    数据接口的读侧校准

    公开(公告)号：US07509223B2

    公开(公告)日：2009-03-24

    申请号：US11735386

    申请日：2007-04-13

    申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    IPC分类号： G06F3/00

    CPC分类号： G01R31/31922 ,  G01R31/3191 ,  G01R31/31937 ,  H04L7/0008 ,  H04L7/0041

    摘要： Circuits, methods and apparatus are provided to reduce skew among signals being received by a data interface. Signal path delays are varied such that data and strobe signals received at a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration circuitry provides skew adjustment of each data signal path by determining one or more delays in each data signal path and strobe signal path based on relative timings of test signals. The rising or falling edges may be used for this alignment.

    摘要翻译： 提供电路，方法和装置以减少由数据接口接收的信号之间的偏差。 变化信号路径延迟使得在存储器接口处接收的数据和选通信号沿着上升沿和/或下降沿彼此校准或对齐。 例如，自校准电路通过基于测试信号的相对定时确定每个数据信号路径和选通信号路径中的一个或多个延迟来提供每个数据信号路径的偏移调整。 上升或下降沿可用于此对齐。

    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
    54.
    发明申请
    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES 有权
    可编程逻辑器件中的写层次实现

    公开(公告)号：US20080201597A1

    公开(公告)日：2008-08-21

    申请号：US11843123

    申请日：2007-08-22

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    IPC分类号： G06F1/12 ,  H04L7/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices
    55.
    发明授权
    Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices 有权
    用于在可编程逻辑器件中提供高效和区域有效的去耦电容的装置和方法

    公开(公告)号：US07309906B1

    公开(公告)日：2007-12-18

    申请号：US11097503

    申请日：2005-04-01

    申请人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

    发明人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

    IPC分类号： H01L29/00 ,  H01L21/8242

    CPC分类号： H01L29/94 ,  H01L27/0203

    摘要： Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.

    摘要翻译： 提供了改进的去耦电容器设计和布局方案，其在比先前已知的去耦电容器设计更高的频率下产生高有效电容和高的面积效率。 改进的去耦电容器设计利用具有较短沟道长度的晶体管栅极来减小沟道的总寄生电阻，从而在较高频率下提供更高的有效电容。 为了实现该去耦电容器设计的更高的面积效率，多余的触点被以栅格或华夫饼形式的多晶硅替代。

    Multiple data rate interface architecture
    57.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US07167023B1

    公开(公告)日：2007-01-23

    申请号：US11059299

    申请日：2005-02-15

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    Loop circuitry with low-pass noise filter
    58.
    发明授权
    Loop circuitry with low-pass noise filter 失效
    具有低通噪声滤波器的回路电路

    公开(公告)号：US07002384B1

    公开(公告)日：2006-02-21

    申请号：US10759915

    申请日：2004-01-16

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    IPC分类号： H03K5/13 ,  H03D3/24

    CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

    摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

    摘要翻译： 提供了用于环路电路（即DLL电路和PLL电路）的相位比较器。 相位比较器包括用于比较参考时钟信号和从产生的环路电路生成的内部时钟信号导出的反馈信号的相位检测器。 相位比较器还包括低通噪声滤波器，用于通过在环路电路的补偿电路之前需要一定的净数量的前导或滞后检测来滤除参考时钟信号和反馈信号之间的错误检测的相位差（即， 调节DLL电路中的受控延迟线或PLL电路中的受控振荡器）。 在进行这些调整之前所需的净测量数取决于提供给相位比较器的可编程带宽信号。

    Programmable I/O element circuit for high speed logic devices
    59.
    发明授权
    Programmable I/O element circuit for high speed logic devices 失效
    用于高速逻辑器件的可编程I / O元件电路

    公开(公告)号：US06853215B1

    公开(公告)日：2005-02-08

    申请号：US10685355

    申请日：2003-10-09

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    IPC分类号： C07K14/47 ,  C07K16/28 ,  H03K19/173

    CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

    摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

    摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速110模式（例如双数据速率和零总线周转）进行操作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

    Multiple data rate interface architecture
    60.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US06806733B1

    公开(公告)日：2004-10-19

    申请号：US10038737

    申请日：2002-01-02

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。