公开(公告)号：US10608431B2

公开(公告)日：2020-03-31

申请号：US15794394

申请日：2017-10-26

Applicant: ANALOG DEVICES, INC.

Inventor： Linfeng He ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H01L27/02 ,  H01L23/528 ,  H01L29/74 ,  G07C5/00 ,  H01L29/06

Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.

公开(公告)号：US10249609B2

公开(公告)日：2019-04-02

申请号：US15674218

申请日：2017-08-10

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Linfeng He

IPC: H01L29/74 ,  H01L31/111 ,  H01L27/02 ,  H01L29/40 ,  H01L29/06

Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar junction transistor (BJT) and a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), where a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT. The integrated circuit device additionally includes a triggering device comprising a first diode having a cathode electrically connected to the base of the first BJT. The integrated circuit device further includes a third BJT cross-coupled with the second BJT to operate as a second SCR, where the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.

公开(公告)号：US09954356B2

公开(公告)日：2018-04-24

申请号：US14797675

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04 ,  H02H9/02 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.

公开(公告)号：US20170366002A1

公开(公告)日：2017-12-21

申请号：US15188626

申请日：2016-06-21

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2924/181 ,  H02H9/044 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.

公开(公告)号：US20170271320A1

公开(公告)日：2017-09-21

申请号：US15614048

申请日：2017-06-05

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  Jonathan Pfeifer

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0207 ,  H01L27/0262

Abstract: The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

公开(公告)号：US20170243862A1

公开(公告)日：2017-08-24

申请号：US15050876

申请日：2016-02-23

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/205 ,  H01L29/872 ,  H01L27/06 ,  H01L29/778

CPC classification number: H01L29/872 ,  H01L27/0285 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1075 ,  H01L29/205 ,  H01L29/7783 ,  H01L29/8124

Abstract: Apparatus and methods for compound semiconductor protection clamps are provided herein. In certain configurations, a compound semiconductor protection clamp includes a resistor-capacitor (RC) trigger network and a metal-semiconductor field effect transistor (MESFET) clamp. The RC trigger network detects when an ESD/EOS event is present between a first node and a second node, and activates the MESFET clamp in response to detecting the ESD/EOS event. When the MESFET clamp is activated, the MESFET clamp provides a low impedance path between the first and second nodes, thereby providing ESD/EOS protection. When deactivated, the MESFET clamp provides high impedance between the first and second nodes, and thus operates with low leakage current and small static power dissipation.

公开(公告)号：US09634482B2

公开(公告)日：2017-04-25

申请号：US14335665

申请日：2014-07-18

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Sandro Herrera

IPC: H02H9/00 ,  H01L27/02 ,  H02H9/02 ,  H02H9/04

CPC classification number: H02H9/005 ,  H01L27/0285 ,  H02H9/046

Abstract: Apparatus and methods for providing transient overstress protection with active feedback are disclosed. In certain configurations, a protection circuit includes a transient detection circuit, a bias circuit, a clamp circuit, and a sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping. The transient detection circuit can detect a presence of a transient overstress event, and can generate a detection current in response to detection of the transient overstress event. The detection current and the positive feedback current can be combined to generate a combined current, and the bias circuit can turn on the clamp circuit in response to the combined current. While the transient overstress event is present and the clamp circuit is clamping, the sense feedback circuit can generate the positive feedback current to maintain the clamp circuit turned on for the event's duration.

公开(公告)号：US09478608B2

公开(公告)日：2016-10-25

申请号：US14546703

申请日：2014-11-18

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  James Zhao ,  Juan Luo

IPC: H01L27/02 ,  H01L23/62 ,  H01L29/06 ,  H01L21/761

CPC classification number: H01L29/0646 ,  H01L21/761 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0259 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/0653 ,  H01L29/73 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure. Additionally, the clamp device includes a first p-type active region and a first n-type active region in the first p-type well region and electrically connected to a first terminal of the clamp device. Furthermore, the clamp device includes a second p-type active region and a second n-type active region in the second p-type well region and electrically connected to a second terminal of the clamp device. The n-type isolation structure is in a p-type region of a semiconductor substrate, and electrically isolates the first and second p-type well regions from the p-type substrate region. The clamp device further includes a blocking voltage tuning structure positioned between the first and second n-type active regions.

Abstract translation: 提供收发器接口过电压钳位的装置和方法。 在某些配置中，接口装置包括n型隔离结构中的第一p型阱区和第二p型阱区。 此外，夹持装置包括第一p型阱区中的第一p型有源区和第一n型有源区，并且电连接到钳位装置的第一端。 此外，夹持装置在第二p型阱区域中包括第二p型有源区和第二n型有源区，并且电连接到钳位装置的第二端。 n型隔离结构在半导体衬底的p型区域中，并将第一和第二p型阱区与p型衬底区电隔离。 钳位装置还包括位于第一和第二n型有源区之间的阻挡电压调谐结构。

公开(公告)号：US20160204096A1

公开(公告)日：2016-07-14

申请号：US14594394

申请日：2015-01-12

Applicant: Analog Devices, Inc.

Inventor： James Zhao ,  Javier Alejandro Salcedo

IPC: H01L27/02 ,  H03K17/567 ,  H01L29/06 ,  H01L21/8222 ,  H01L49/02 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L21/8222 ,  H01L28/20 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/861 ,  H03K17/567

Abstract: Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region, a second p-well region, and an n-well region positioned between the first and second p-wells regions. The bidirectional clamp further includes two or more oxide regions over the n-well region, and one or more n-type active (N+) dummy blocking current regions are positioned between the oxide regions. The one or more N+ dummy leakage current blocking regions interrupt an electrical path from the first p-type well region to the second p-type well region along interfaces between the n-well region and the oxide regions. Thus, even when charge accumulates at the interfaces due to extended high voltage, e.g., >60V, and/or high temperature operation (e.g., >125° C.), the N+ dummy leakage current blocking regions inhibit charge trapping-induced leakage current.

Abstract translation: 提供了低泄漏双向夹具及其形成方法。 在某些配置中，双向钳位包括第一p阱区，第二p阱区和位于第一和第二p阱区之间的n阱区。 双向夹具还包括在n阱区域上的两个或更多个氧化物区域，并且一个或多个n型有源（N +）虚拟阻挡电流区域位于氧化物区域之间。 一个或多个N +虚设泄漏电流阻断区域沿着n阱区域和氧化物区域之间的界面中断从第一p型阱区域到第二p型阱区域的电路径。 因此，即使当由于延长的高电压（例如> 60V）和/或高温操作（例如> 125℃）在接口处累积电荷时，N +虚设泄漏电流阻挡区域抑制电荷捕获诱发的漏电流 。

公开(公告)号：US09356011B2

公开(公告)日：2016-05-31

申请号：US14446205

申请日：2014-07-29

Applicant: Analog Devices, Inc.

Inventor： David J. Clarke ,  Javier Alejandro Salcedo ,  Brian B. Moane ,  Juan Luo ,  Seamus Murnane ,  Kieran K. Heffernan ,  John Twomey ,  Stephen Denis Heffernan ,  Gavin Patrick Cosgrave

IPC: H01L29/747 ,  H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L27/06 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L27/0635 ,  H01L27/0647 ,  H01L29/0692 ,  H01L29/66386 ,  H01L29/7412 ,  H01L29/747

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract translation: 提供了隔离隔离电压装置及其形成方法。 在某些实施方案中，阻断电压装置包括电连接到第一p阱的阳极端子，电连接到第一n阱的阴极端子，电连接到第二p阱的接地端子，以及n型 用于将第一p阱与p型衬底隔离的隔离层。 第一个p阱和第一个n阱作为阻塞二极管工作。 阻断电压装置还包括与形成在第一n阱，第一n阱，第一p阱以及形成在第一p阱中的N +区相关的PN +可控硅整流器（SCR） 。 另外，阻断电压装置还包括与形成在第一p阱，第一p阱，n型隔离层，第二p阱以及形成在第一p阱中的N +区域相关联的N +区域的NPNPN双向SCR 第二个p井。