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102 条记录 (耗时 0.051 秒)

    Scan register and methods of using the same
    53.
    发明授权
    Scan register and methods of using the same 有权
    扫描寄存器和使用方法

    公开(公告)号：US07457998B1

    公开(公告)日：2008-11-25

    申请号：US11033059

    申请日：2005-01-07

    申请人： Sandeep Bhatia ,  Oriol Roig

    发明人： Sandeep Bhatia ,  Oriol Roig

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541

    摘要： An improved scan register and methods of using the same have been disclosed. In one embodiment, the improved scan register includes a master latch having a data input, a data output, and a control input. The control input is coupled to a clock signal. The master latch is operable to store data. The improved scan register further includes a scan latch having a data input, a data output, and a control input. The data input of the scan latch is coupled to the data output of the master latch. The scan latch is operable to receive and to store the data from the master latch in response to the scan latch being in a scan mode. The improved scan register may further include a functional latch having a data input, a data output, and a control input. The data input of the functional latch is coupled to the data output of the master latch. The functional latch is operable to receive and to store the data from the master latch in response to the functional latch being in a functional mode. Other embodiments have been claimed and described.

    摘要翻译： 已经公开了改进的扫描寄存器及其使用方法。 在一个实施例中，改进的扫描寄存器包括具有数据输入，数据输出和控制输入的主锁存器。 控制输入​​耦合到时钟信号。 主锁存器可操作以存储数据。 改进的扫描寄存器还包括具有数据输入，数据输出和控制输入的扫描锁存器。 扫描锁存器的数据输入耦合到主锁存器的数据输出端。 响应于扫描锁存器处于扫描模式，扫描锁存器可操作以接收并存储来自主锁存器的数据。 改进的扫描寄存器还可以包括具有数据输入，数据输出和控制输入的功能锁存器。 功能锁存器的数据输入耦合到主锁存器的数据输出端。 响应于功能锁存器处于功能模式，功能锁存器可操作以接收并存储来自主锁存器的数据。 已经要求和描述了其它实施例。

    Two address map for transactions between an X-bit processor and a Y-bit wide memory
    54.
    发明授权
    Two address map for transactions between an X-bit processor and a Y-bit wide memory 有权
    两个X位处理器和Y位宽存储器之间的事务地址映射

    公开(公告)号：US07360055B2

    公开(公告)日：2008-04-15

    申请号：US10776760

    申请日：2004-02-10

    申请人： Sandeep Bhatia

    发明人： Sandeep Bhatia

    IPC分类号： G06F12/06

    CPC分类号： G06F13/4018

    摘要： Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises a first address space, a second address space, and a bridge. The first address space stores data words of a first length. The second address space stores data words of a second length. The bridge performs one transaction after receiving a transaction with an address corresponding to the first address space and performs two transactions after receiving a transaction with the address corresponding to the second address space.

    摘要翻译： 这里提出了用于X位处理器和Y位宽存储器之间的事务的两个地址映射的系统和方法。 处理器子系统包括第一地址空间，第二地址空间和桥。 第一地址空间存储第一长度的数据字。 第二地址空间存储第二长度的数据字。 在接收到具有与第一地址空间相对应的地址的事务之后，桥接器执行一个事务，并且在接收到与第二地址空间相对应的地址的事务之后执行两个事务。