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公开(公告)号：US06853385B1
公开(公告)日：2005-02-08
申请号：US09641374
申请日：2000-08-18
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/397 , G09G5/42 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/81 , H04L12/28 , H04N11/00 , H04N11/22
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
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公开(公告)号：US20100103195A1
公开(公告)日：2010-04-29
申请号：US12650361
申请日：2009-12-30
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US07667715B2
公开(公告)日：2010-02-23
申请号：US11498595
申请日：2006-08-03
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US07110006B2
公开(公告)日：2006-09-19
申请号：US10997652
申请日：2004-11-23
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
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公开(公告)号：US08022966B2
公开(公告)日：2011-09-20
申请号：US12650361
申请日：2009-12-30
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US09077997B2
公开(公告)日：2015-07-07
申请号：US10763087
申请日：2004-01-22
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F3/00 , H04N19/436 , G06T9/00 , G09G5/00 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , H04N5/04 , H04N5/14 , H04N5/445 , H04N5/45 , H04N7/01 , H04N9/45 , H04N9/64 , H04N21/422 , H04N21/43 , H04N21/426 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/423 , H04N19/59 , G09G5/02 , H04N5/12 , H04N5/44 , H04N5/46 , H04N11/14 , H04N11/20
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
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7.发明申请Graphics Display System with Anti-Flutter Filtering and Vertical Scaling Feature 审中-公开具有防抖动滤波和垂直缩放功能的图形显示系统公开(公告)号：US20120268655A1
公开(公告)日：2012-10-25
申请号：US13453243
申请日：2012-04-23
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
CPC分类号： G06F16/9577
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片处理模拟视频输入，数字视频输入和图形输入。 该芯片包括单个多相滤波器，其优选地提供图像的防颤音滤波和缩放。 防颤音滤波可能有助于减少由于电视显示器的隔行特性引起的显示闪烁。 图形的缩放可以用于将图形的正方形像素长宽比转换为视频的正常矩形像素长宽比。
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公开(公告)号：US08078981B2
公开(公告)日：2011-12-13
申请号：US12268036
申请日：2008-11-10
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。 该芯片处理组织为Windows的图形图像。 芯片获取描述窗口的数据，根据显示器上窗口的深度对数据进行排序，从存储器传输图形图像，并使用与图形图像相关联的alpha值对图形图像进行混合。
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公开(公告)号：US07209992B2
公开(公告)日：2007-04-24
申请号：US10762975
申请日：2004-01-22
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。 图形显示系统处理模拟视频输入，数字视频输入和图形输入。 该系统包含由图形系统，CPU和其他外围设备共享的统一存储器架构。 统一存储器架构使用实时调度来服务任务。 关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划，同时根据需要为非实时任务进行服务。
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公开(公告)号：US07057622B2
公开(公告)日：2006-06-06
申请号：US10423364
申请日：2003-04-25
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.
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