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    INTEGRATED CIRCUIT BUFFER DEVICE
    52.
    发明申请
    INTEGRATED CIRCUIT BUFFER DEVICE 失效
    集成电路缓冲器器件

    公开(公告)号：US20060067141A1

    公开(公告)日：2006-03-30

    申请号：US10625276

    申请日：2003-07-23

    申请人： Richard Perego ,  Stefanos Sidiropoulos ,  Ely Tsern

    发明人： Richard Perego ,  Stefanos Sidiropoulos ,  Ely Tsern

    IPC分类号： G11C7/00

    CPC分类号： G11C29/028 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50012 ,  Y02D10/14

    摘要： A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link

    摘要翻译： 存储器系统架构/互连拓扑，其包括主机和至少一个存储器子系统之间的至少一个点对点链路。 存储器子系统包括耦合到多个存储器件的缓冲器件。 可以通过专用点对点链路和对应的存储器子系统升级存储器系统。 主设备经由每个点到点链路通过相应的缓冲设备与每个存储器子系统中的多个存储器件进行通信

    System and method for aligning internal transmit and receive clocks
    53.
    发明申请
    System and method for aligning internal transmit and receive clocks 审中-公开
    用于对准内部发送和接收时钟的系统和方法

    公开(公告)号：US20050220235A1

    公开(公告)日：2005-10-06

    申请号：US11130506

    申请日：2005-05-16

    申请人： Donald Stark ,  Jun Kim ,  Stefanos Sidiropoulos

    发明人： Donald Stark ,  Jun Kim ,  Stefanos Sidiropoulos

    IPC分类号： H04J3/06 ,  H04L7/00 ,  H04L7/02

    CPC分类号： H04L7/0008 ,  G06F13/4072 ,  G11C7/1003 ,  G11C7/222 ,  H04L7/02

    摘要： A system includes a master device connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master device. A delay locked loop circuit receives the first system clock and a second phase feedback signal as inputs and generates a transmit clock signal. A phase offset circuit receives the transmit system clock and generates a phase shifted version of the transmit clock signal as a second system clock. A first phase detector receives a receive system clock and the transmit system clock and generates a first phase feedback signal. A delay element receives the first system clock and the first phase feedback signal and generates a delayed first system clock. A second phase detector receives the delayed first system clock and the second system clock and generates the second phase feedback signal.

    摘要翻译： 系统包括经由信道连接到一个或多个从设备的主设备，该信道将外部产生的第一系统时钟传送到主设备。 延迟锁定环电路接收第一系统时钟和第二相位反馈信号作为输入，并产生发送时钟信号。 相位偏移电路接收发射系统时钟并产生作为第二系统时钟的发送时钟信号的相移版本。 第一相位检测器接收接收系统时钟和发射系统时钟并产生第一相位反馈信号。 延迟元件接收第一系统时钟和第一相位反馈信号并产生延迟的第一系统时钟。 第二相位检测器接收延迟的第一系统时钟和第二系统时钟并产生第二相位反馈信号。

    Memory module having an integrated circuit buffer device
    54.
    发明申请
    Memory module having an integrated circuit buffer device 失效
    具有集成电路缓冲器的存储器模块

    公开(公告)号：US20050210196A1

    公开(公告)日：2005-09-22

    申请号：US11128904

    申请日：2005-05-13

    申请人： Richard perego ,  Stefanos Sidiropoulos ,  Ely Tsern

    发明人： Richard perego ,  Stefanos Sidiropoulos ,  Ely Tsern

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C7/10 ,  G11C29/02

    CPC分类号： G11C29/028 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50012

    摘要： A memory module includes an integrated circuit buffer device that receives control information via a connector interface. A first plurality of signal lines carries a first address from the integrated circuit buffer device to a first memory device. A second plurality of signal lines carries a first control signal from the integrated circuit buffer device to the first memory device. The first control signal specifies a read operation by the first memory device such that the first memory device provides first data, accessed from a memory location in the first memory device based on the first address, to the integrated circuit buffer device. A first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A third plurality of signal lines carries a second address from the integrated circuit device to the second memory device. A fourth plurality of signal lines carries a second control signal from the integrated circuit buffer device to the second memory device. The second control signal specifies a read operation. The second control signal corresponds to the control information. A second signal line carries a second signal from the integrated circuit buffer device to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device. A transmitter circuit is disposed on the integrated circuit buffer device.

    摘要翻译： 存储器模块包括经由连接器接口接收控制信息的集成电路缓冲器装置。 第一多个信号线将第一地址从集成电路缓冲器装置传送到第一存储器件。 第二多个信号线将集成电路缓冲器件的第一控制信号传送到第一存储器件。 第一控制信号指定第一存储器件的读取操作，使得第一存储器件提供从基于第一地址的第一存储器件中的存储器位置访问的第一数据到集成电路缓冲器件。 第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。 第一信号使来自集成电路缓冲器的第一控制信号与第一存储器件的通信同步。 第三组信号线将第二地址从集成电路装置传送到第二存储装置。 第四多个信号线将集成电路缓冲器装置的第二控制信号传送到第二存储装置。 第二控制信号指定读操作。 第二控制信号对应于控制信息。 第二信号线将来自集成电路缓冲器装置的第二信号传送到第二存储装置。 第二信号使来自集成电路缓冲器的第二控制信号与第二存储器件的通信同步。 发射机电路设置在集成电路缓冲装置上。

    Repeate architecture with single clock multiplier unit
    57.
    发明授权
    Repeate architecture with single clock multiplier unit 有权
    具有单时钟倍频单元的中继器架构

    公开(公告)号：US08638896B2

    公开(公告)日：2014-01-28

    申请号：US12728129

    申请日：2010-03-19

    申请人： Dean Liu ,  Marc J. Loinaz ,  Stefanos Sidiropoulos

    发明人： Dean Liu ,  Marc J. Loinaz ,  Stefanos Sidiropoulos

    IPC分类号： H04L7/00

    CPC分类号： H03L7/18 ,  H03L7/081

    摘要： A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.

    摘要翻译： 用于时钟的电路包括输入数据路径，接收器，一组触发器，至少一个内插器和控制器。 接收器耦合到输入数据路径以接收输入数据。 耦合到接收器的触发器对输入数据进行采样。 耦合到一个或多个触发器的第一内插器接收采样的输入数据。 耦合到第一内插器的控制器通过向第一内插器提供关于输入数据的相位信息来控制第一内插器。 该电路减少了从输入路径传输到输出路径的任何抖动。

    Methods and apparatus for clock and data recovery using transmission lines
    58.
    发明授权
    Methods and apparatus for clock and data recovery using transmission lines 有权
    使用传输线的时钟和数据恢复的方法和装置

    公开(公告)号：US08599983B2

    公开(公告)日：2013-12-03

    申请号：US13351956

    申请日：2012-01-17

    申请人： Stefanos Sidiropoulos ,  Haw-Jyh Liaw

    发明人： Stefanos Sidiropoulos ,  Haw-Jyh Liaw

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0008 ,  H04L7/0337 ,  H04L25/068

    摘要： A clock and data recovery circuit may comprise a first transmission line comprising a plurality of segments of a first predetermined length. The first transmission line receives and propagates a clock signal through the segments of the first predetermined length. The clock and data recovery circuit may further comprise a second transmission line comprising a plurality of segments of a second predetermined length. The second transmission line receives data from a serial bit stream and propagates the data through the segments of the second predetermined length. In some embodiments, the first or second transmission line further comprise taps to extract, from the segments of the second predetermined length, a plurality of delayed data signals. The clock and data recovery circuit may further comprise a plurality of sampling circuits, coupled to the first and second transmission lines, to generate samples from the delayed data signals and the delayed clock signals.

    摘要翻译： 时钟和数据恢复电路可以包括包括第一预定长度的多个段的第一传输线。 第一传输线通过第一预定长度的段接收和传播时钟信号。 时钟和数据恢复电路还可以包括包括第二预定长度的多个段的第二传输线。 第二传输线从串行比特流接收数据，并通过第二预定长度的段传播数据。 在一些实施例中，第一或第二传输线还包括从第二预定长度的段提取多个延迟的数据信号的抽头。 时钟和数据恢复电路还可以包括耦合到第一和第二传输线的多个采样电路，以从延迟的数据信号和延迟的时钟信号产生采样。

    Systems, circuits and methods for filtering signals to compensate for channel effects
    59.
    发明授权
    Systems, circuits and methods for filtering signals to compensate for channel effects 有权
    用于滤波信号以补偿信道效应的系统，电路和方法

    公开(公告)号：US08537949B1

    公开(公告)日：2013-09-17

    申请号：US12828153

    申请日：2010-06-30

    申请人： Halil Cirit ,  Stefanos Sidiropoulos

    发明人： Halil Cirit ,  Stefanos Sidiropoulos

    IPC分类号： H04L7/00

    CPC分类号： H04B10/2507 ,  H04L25/03063 ,  H04L25/0307 ,  H04L25/03076

    摘要： Transmitter waveform dispersion penalty (“TWDP”) is decreased in a transmitter. A binary data signal is received for transmission over a channel that exhibits TWDP. The data signal is shifted less than a full clock cycle to generate at least one post cursor signal. The post cursor signal is subtracted from the data signal to generate a transmitter output data signal for transmission over the channel. In addition to decreasing TWDP, data dependent jitter is also reduced for data transmission across a channel that exhibits a multi-pole transmission characteristic. A main data signal and at least one cursor signal, which is shifted at least a portion of a clock period from the main data signal, is generated. The cursor signal is filtered to filter out effects based on the second pole of the multi-pole transmission characteristic. The main data signal is subtracted from the filtered cursor signal to generate the transmitter output data signal. Circuits and methods for transmitting serial data streams over a channel compliant with KR and SPI specifications are also disclosed.

    摘要翻译： 发射机中的发射机波形色散损失（“TWDP”）减小。 接收二进制数据信号以通过展现TWDP的信道进行传输。 数据信号被移动小于一整个时钟周期以产生至少一个后光标信号。 从数据信号中减去后光标信号，以产生用于在信道上传输的发射机输出数据信号。 除了降低TWDP之外，数据相关的抖动也减少了跨越显示多极传输特性的通道的数据传输。 产生主数据信号和至少一个光标信号，其被从主数据信号的至少一部分时钟周期移位。 对光标信号进行滤波以滤除基于多极传输特性的第二极点的效果。 从经滤波的光标信号中减去主数据信号，以产生发射机输出数据信号。 还公开了通过符合KR和SPI规范的信道发送串行数据流的电路和方法。

    Multi-value logic signaling in multi-functional circuits
    60.
    发明授权
    Multi-value logic signaling in multi-functional circuits 有权
    多功能电路中的多值逻辑信号

    公开(公告)号：US08520744B2

    公开(公告)日：2013-08-27

    申请号：US12728113

    申请日：2010-03-19

    申请人： Marc Loinaz ,  Stefanos Sidiropoulos ,  Whay Sing Lee

    发明人： Marc Loinaz ,  Stefanos Sidiropoulos ,  Whay Sing Lee

    IPC分类号： H04B3/00

    CPC分类号： H03L5/00 ,  G01R31/2851 ,  G06F7/00 ,  G06F21/00 ,  H03K19/0002

    摘要： Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

    摘要翻译： 方法和电路为受限制的一组通信线路上的多功能电路提供功能适当的信号。 第一通信线路接收数字信号。 第二通信线路用于与第一功能有关的数字信号。 在另外的步骤中，该方法包括基于第一通信线路上的多值逻辑数字信号启动产生二次功能激活信号的激活过程。 在接收到第二功能激活信号时，第二通信线路用于与第二功能相关的数字信号。 优选的激活过程包括监视用于数字签名的第二通信线路，并且在检测到适当的签名时发送激活信号。