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51.发明授权Methods of depositing a layer comprising tungsten and methods of forming a transistor gate line 有权沉积包含钨的层的方法和形成晶体管栅极线的方法公开(公告)号：US06617250B2
公开(公告)日：2003-09-09
申请号：US10243406
申请日：2002-09-13
IPC分类号： H01L21302
CPC分类号： H01L21/31122 , H01L21/28061 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/31604 , H01L21/32051 , H01L27/10811 , H01L27/10888 , H01L28/90 , H01L29/6659
摘要： In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate. In one implementation, the layer is exposed to WF6 under conditions effective to both etch substantially amorphous Ta2O5 from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.
摘要翻译： 部分地，公开了半导体处理方法，在衬底上沉积含钨层的方法，在衬底上沉积含氮化钨的层的方法，在衬底上沉积包含硅化钨的层的方法，形成晶体管栅极的方法 在衬底上划线，形成图案化的基本上结晶的Ta 2 O 5的材料的方法，以及形成包含基本上结晶的Ta 2 O 5的材料的电容器电介质区域的方法。 在一个实施方案中，半导体处理方法包括在半导体衬底上形成包含基本非晶态的Ta 2 O 5层。 该层在有效从底物上蚀刻基本无定形Ta 2 O 5的条件下暴露于WF6。 在一个实施方案中，该层在有效地从衬底上蚀刻基本上无定形Ta 2 O 5的条件下暴露于WF6，并在曝光期间在衬底上沉积含钨层。
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公开(公告)号：US06589839B1
公开(公告)日：2003-07-08
申请号：US09522627
申请日：2000-03-10
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/3105 , H01L28/84
摘要： A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.
摘要翻译： 独特的电化学过程填充电介质中的氧空位，同时减少附近电极和导体的氧化。 优选地，将电磁场或偏压施加到电介质。 偏压导致电介质中的氧空位迁移到电介质的表面。 当氧空位向表面迁移时，氧离子填充氧空位。 在一个实施例中，独特的等离子体处理提供与氧空位反应的氧离子。 在另一个实施方案中，独特的电解处理提供与氧空位反应的氧离子。
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53.发明授权Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权向源极/漏极区形成导电接触的方法以及形成局部互连的方法公开(公告)号：US08084142B2
公开(公告)日：2011-12-27
申请号：US11525762
申请日：2006-09-21
IPC分类号： H01L21/44 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。 在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。 至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。 接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。 考虑了其他方面和实现。
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54.发明授权公开(公告)号：US07923308B2
公开(公告)日：2011-04-12
申请号：US11478715
申请日：2006-06-30
IPC分类号： H01L21/332 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
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55.发明申请Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor 有权形成包含外延硅和场效应晶体管的层的方法公开(公告)号：US20100258857A1
公开(公告)日：2010-10-14
申请号：US12820924
申请日：2010-06-22
IPC分类号： H01L29/78
CPC分类号： H01L29/66787 , H01L21/0237 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L29/66742 , H01L29/78642
摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括形成包括外延硅和场效应晶体管的层的方法。 在一个实施方案中，形成包含外延硅的层的方法包括从暴露的单晶材料外延生长含硅层。 外延生长的硅包括以不超过1原子％的总浓度存在的碳，锗和氧中的至少一种。 在一个实施方案中，该层包括含有至少1原子％锗的硅锗合金，并且还包含总浓度不大于1原子％的碳和氧中的至少一种。 考虑了其他方面和实现。
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公开(公告)号：US07768036B2
公开(公告)日：2010-08-03
申请号：US12410179
申请日：2009-03-24
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/66787 , H01L21/0237 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L29/66742 , H01L29/78642
摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括形成包括外延硅和场效应晶体管的层的方法。 在一个实施方案中，形成包含外延硅的层的方法包括从暴露的单晶材料外延生长含硅层。 外延生长的硅包括以不超过1原子％的总浓度存在的碳，锗和氧中的至少一种。 在一个实施方案中，该层包括含有至少1原子％锗的硅锗合金，并且还包含总浓度不大于1原子％的碳和氧中的至少一种。 考虑了其他方面和实现。
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57.发明授权Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 失效向源极/漏极区形成导电接触的方法以及形成局部互连的方法公开(公告)号：US07572710B2
公开(公告)日：2009-08-11
申请号：US11525707
申请日：2006-09-21
IPC分类号： H01L21/338 , H01L21/337 , H01L21/8238 , H01L21/8234 , H01L21/8242 , H01L21/8222 , H01L21/20 , H01L21/4763
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。 在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。 至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。 接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。 考虑了其他方面和实现。
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公开(公告)号：US07550345B2
公开(公告)日：2009-06-23
申请号：US11485593
申请日：2006-07-11
申请人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
发明人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
IPC分类号： H01L21/20
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/1272 , H01L21/31645 , H01L27/10852 , H01L28/60 , H01L28/65 , H01L28/90 , H01L28/91 , H01L29/7833
摘要： The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.
摘要翻译： 本发明包括形成含铪材料的方法，例如氧化铪。 在一个方面，提供了半导体衬底，并且利用第一反应条件来形成在衬底上所需的结晶相和取向的含铪种子材料。 随后，利用第二反应条件在种子材料上生长第二含铪材料。 第二含铪材料处于与含铪种子材料的结晶相和取向不同的结晶相和/或取向。 第二含铪材料可以是例如非晶相。 然后将种子材料用于在第二含铪材料中诱导所需的结晶相和取向。 本发明还包括使用含铪材料的电容器结构和包括电容器结构的电路组件。
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公开(公告)号：US07498057B2
公开(公告)日：2009-03-03
申请号：US11075017
申请日：2005-03-08
申请人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
发明人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
IPC分类号： C23C16/04
CPC分类号： C23C16/45519 , C23C16/4401 , C23C16/455
摘要： A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.
摘要翻译： 沉积方法包括将基板定位在至少部分地由室壁限定的沉积室内。 所述室壁中的至少一个包括腔室表面，其中具有多个吹扫气体入口。 在衬底上设置工艺气体，有效地将层沉积到衬底上。 在这种提供过程中，材料粘附到室表面。 反应性净化气体从吹扫气体入口排出到沉积室，有效地在室表面上形成反应性气体帘幕并远离衬底，这种反应性气体与这种粘附材料反应。 考虑进一步的实现。
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公开(公告)号：US07442977B2
公开(公告)日：2008-10-28
申请号：US11253461
申请日：2005-10-19
IPC分类号： H01L27/108
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。
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