公开(公告)号：US20120220113A1

公开(公告)日：2012-08-30

申请号：US13033616

申请日：2011-02-24

申请人： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

发明人： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966

摘要： The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

摘要翻译： 本发明提供一种制造具有金属栅极的半导体器件的方法。 首先，提供基板。 具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。 去除第一牺牲栅极以形成第一沟槽，然后在第一沟槽中形成第一金属层和第一材料层。 接下来，第一金属层和第一材料层变平。 去除第二牺牲栅极以形成第二沟槽，然后在第二沟槽中形成第二金属层和第二材料层。 最后，第二金属层和第二材料层变平。

公开(公告)号：US07544623B2

公开(公告)日：2009-06-09

申请号：US11530886

申请日：2006-09-11

申请人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76802 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/31144

摘要： A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB) layer is then coated on the etching resistive layer. A photoresist layer is then coated on the SHB layer. A lithographic process is performed to form a first opening in the photoresist layer. Using the photoresist layer as a hard mask, the SHB layer is etched through the first opening, thereby forming a shrunk, tapered second opening in the SHB layer. Using the etching resistive layer as an etching hard mask, etching the dielectric layer through the second opening to form a contact hole in the dielectric layer.

摘要翻译： 提供一种制造接触孔的方法。 制备其上具有导电区域的半导体衬底。 介电层沉积在半导体衬底和导电区域上。 在电介质层上涂覆有蚀刻电阻层。 然后将含硅硬掩模底部防反射涂层（SHB）层涂覆在蚀刻电阻层上。 然后将光致抗蚀剂层涂覆在SHB层上。 执行光刻工艺以在光致抗蚀剂层中形成第一开口。 使用光致抗蚀剂层作为硬掩模，通过第一开口蚀刻SHB层，从而在SHB层中形成收缩的锥形第二开口。 使用蚀刻电阻层作为蚀刻硬掩模，通过第二开口蚀刻电介质层，以在电介质层中形成接触孔。

公开(公告)号：US20080182070A1

公开(公告)日：2008-07-31

申请号：US11669168

申请日：2007-01-31

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/302 ,  B32B3/10

CPC分类号： B82Y10/00 ,  B81C99/009 ,  B82Y40/00 ,  G03F7/0002 ,  H01L33/44 ,  H01L2933/0083 ,  Y10T428/24331

摘要： The method of manufacturing an imprinting template according to the present invention utilizes a semiconductor manufacturing process and comprises a step of etching an oxide layer having a thickness of from 1000 to 8000 angstroms on a substrate by a microlithography and etching process, to form a pattern having a plurality of pillar-shaped holes, thereby forming an imprinting plate having a plurality of pillar-shaped holes. A material layer may be filled into the holes and a part of the oxide layer is removed to form an imprinting template having a plurality of pillar-shaped protrusions. Alternatively, a silicon substrate may be used instead of the substrate and the oxide layer. The imprinting template according to the present invention has advantages of mass production, fast production, and low cost, and is suitable to serve as the imprinting plate for making photonic crystals.

摘要翻译： 根据本发明的制造压印模板的方法利用半导体制造工艺，并且包括通过微光刻和蚀刻工艺在衬底上蚀刻具有1000至8000埃厚度的氧化物层的步骤，以形成具有 多个柱状孔，从而形成具有多个柱状孔的压印板。 可以将材料层填充到孔中，并且去除氧化物层的一部分以形成具有多个柱状突起的压印模板。 或者，可以使用硅衬底代替衬底和氧化物层。 根据本发明的压印模板具有批量生产，快速生产和低成本的优点，并且适合用作制造光子晶体的压印板。

公开(公告)号：US09384962B2

公开(公告)日：2016-07-05

申请号：US13082387

申请日：2011-04-07

申请人： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

发明人： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC分类号： H01L21/28 ,  H01L21/02

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

摘要翻译： 提供一种制造金属栅极的方法。 该方法包括提供基板。 然后，在基板上形成栅极电介质层。 在栅极电介质层上形成具有功函数金属层的多层堆叠结构。 在多层堆叠结构的至少一层上进行O2气氛处理。 在多层堆叠结构上形成导电层。

公开(公告)号：US08691652B2

公开(公告)日：2014-04-08

申请号：US13463809

申请日：2012-05-03

申请人： Lung-En Kuo ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen

发明人： Lung-En Kuo ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66795

摘要： A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed.

摘要翻译： 半导体工艺包括以下步骤。 在基板上形成翅片状结构。 形成栅极结构和盖层，其中栅极结构设置在鳍状结构的一部分和基板的一部分之间，盖层在栅极结构上，并且盖层包括第一盖层 栅极结构和第一盖层上的第二盖层。 形成间隔材料以完全覆盖第二盖层，鳍状结构和基底。 间隔物材料被蚀刻，使得第二盖层的侧壁被暴露，并且在栅极结构旁边形成间隔物。 第二盖层被去除。

公开(公告)号：US20130109151A1

公开(公告)日：2013-05-02

申请号：US13281459

申请日：2011-10-26

申请人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

发明人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

摘要翻译： 公开了一种形成没有空隙的电介质层的方法。 首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。 第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。 然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。 然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

公开(公告)号：US08236702B2

公开(公告)日：2012-08-07

申请号：US12042340

申请日：2008-03-05

申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.

摘要翻译： 提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。 然后对电介质层和蚀刻停止层进行图案化以形成暴露半导体衬底的多个开口。 随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。 然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

公开(公告)号：US20120184105A1

公开(公告)日：2012-07-19

申请号：US13431945

申请日：2012-03-27

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338

摘要： A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.

摘要翻译： 提供一种形成开口的方法。 首先，提供其上具有含硅光刻胶层的基板。 其次，在含硅光致抗蚀剂层上形成第一光刻胶图案。 然后，通过使用第一光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第一蚀刻步骤以形成多个第一开口。 接下来，在含硅光致抗蚀剂层上形成第二光致抗蚀剂图案。 然后，通过使用第二光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第二蚀刻步骤以形成多个第二开口。

公开(公告)号：US20110294075A1

公开(公告)日：2011-12-01

申请号：US12786794

申请日：2010-05-25

申请人： Shin-Chi Chen ,  Jiunn-Hsiung Liao

发明人： Shin-Chi Chen ,  Jiunn-Hsiung Liao

IPC分类号： G03F7/20

CPC分类号： H01L21/0337

摘要： A patterning method of the present invention is described as follows. A mask layer and a patterned photoresist layer are formed on a target layer in sequence, wherein an etching rate of the mask layer is different from an etching rate of the target layer. A plurality of spacers is formed on sidewalls of the patterned photoresist layer respectively, wherein an etching rate of the spacers is different from the etching rate of the mask layer. The patterned photoresist layer is removed to form an opening between any two adjacent spacers. A portion of the mask layer is removed by using the spacers as a mask so as to form a patterned mask layer. A portion of the target layer is removed by using the patterned mask layer as a mask.

摘要翻译： 本发明的图案形成方法如下所述。 掩模层和图案化的光致抗蚀剂层依次形成在目标层上，其中掩模层的蚀刻速率与目标层的蚀刻速率不同。 分别在图案化的光致抗蚀剂层的侧壁上形成多个间隔物，其中间隔物的蚀刻速率与掩模层的蚀刻速率不同。 去除图案化的光致抗蚀剂层以形成任何两个相邻间隔物之间​​的开口。 通过使用间隔物作为掩模去除掩模层的一部分，以形成图案化掩模层。 通过使用图案化掩模层作为掩模来去除目标层的一部分。

公开(公告)号：US20110223768A1

公开(公告)日：2011-09-15

申请号：US12720671

申请日：2010-03-10

申请人： Ying-Chih LIN ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Chih-Wen Feng ,  Shang-Yuan Tsai

发明人： Ying-Chih LIN ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Chih-Wen Feng ,  Shang-Yuan Tsai

IPC分类号： H01L21/311

CPC分类号： H01L21/31116 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76814

摘要： A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas.

摘要翻译： 提供了形成接触开口的方法。 首先，在基板上形成半导体装置。 接下来，在衬底上依次形成蚀刻停止层，第一电介质层和图案化光致抗蚀剂层。 接下来，去除第一电介质层的一部分和蚀刻停止层的一部分以形成开口，其中第一介电层的一部分和蚀刻停止层的部分不被图案化的光致抗蚀剂层覆盖。 接下来，去除图案化的光致抗蚀剂层。 接下来，进行过蚀刻处理以去除开口底部的蚀刻停止层，并在无氮环境中暴露半导体器件。 过蚀刻工艺的反应气体包括含氟烃，氢气和氩气。