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    Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
    51.
    发明授权
    Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
    在存储器单元的电容器阵列上形成位线的方法以及存储器单元的电容器阵列上的位线阵列

    公开(公告)号：US6110774A

    公开(公告)日：2000-08-29

    申请号：US920621

    申请日：1997-08-27

    申请人： Mark Jost ,  Charles Dennison

    发明人： Mark Jost ,  Charles Dennison

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

    摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

    摘要翻译： 半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于位线和另一个有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和 内部存储节点上表面。 还公开了一种制造这种结构的方法。

    Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate
    52.
    发明授权
    Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate 失效
    在半导体衬底内形成互补的n型掺杂和p型掺杂有源区的半导体处理方法

    公开(公告)号：US5970335A

    公开(公告)日：1999-10-19

    申请号：US797547

    申请日：1997-02-07

    申请人： Mark Helm ,  Charles Dennison

    发明人： Mark Helm ,  Charles Dennison

    IPC分类号： H01L21/8238 ,  H01L21/8239

    CPC分类号： H01L21/823871 ,  H01L27/1052 ,  Y10S148/123

    摘要： A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate; c) providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region; d) patterning the insulating layer to provide a void therethrough to the desired first conductivity type region; e) filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3, the desired first conductivity type region having a first conductivity type dopant concentration prior to the filling step which is in the range of from 0 ions/cm.sup.3 to 1.times.10.sup.19 ions/cm.sup.3 ; and f) annealing the substrate for a period of time effective to out-diffuse first conductivity type dopant impurity from the first conductivity type doped polysilicon plug into the substrate to form the desired first conductivity type active region having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3 in the substrate. Methods of forming CMOS FET transistors, and SRAM and DRAM CMOS circuitry are also disclosed.

    摘要翻译： 在半导体衬底内形成互补的第一导电类型掺杂和第二导电类型掺杂有源区的半导体处理方法包括：a）提供半导体衬底; b）掩蔽所述衬底的期望的第一导电类型区域，同时将第二导电类型掺杂到所述衬底的期望的第二导电类型有源区; c）在期望的第一导电类型区域和第二导电类型掺杂区域上的衬底上方提供绝缘层; d）图案化绝缘层以提供穿过其到期望的第一导电类型区域的空隙; e）用第一导电型掺杂多晶硅插塞填充空隙，所述插塞具有至少1×10 20个离子/ cm 3的第一导电类型掺杂剂杂质浓度，所述第一导电类型区域在填充步骤之前具有第一导电类型掺杂剂浓度 其范围为0离子/ cm 3至1×10 19离子/ cm 3; 以及f）使所述衬底退火一段时间以有效地将第一导电类型的掺杂杂质从所述第一导电型掺杂多晶硅插塞扩散到所述衬底中，以形成所述第一导电类型有源区，所述第一导电类型的掺杂杂质浓度为 在衬底中至少1×1020离子/ cm3。 还公开了形成CMOS FET晶体管，以及SRAM和DRAM CMOS电路的方法。

    Planar thin film transistor structures
    53.
    发明授权
    Planar thin film transistor structures 失效
    平面薄膜晶体管结构

    公开(公告)号：US5844254A

    公开(公告)日：1998-12-01

    申请号：US858863

    申请日：1997-05-19

    申请人： Monte Manning ,  Charles Dennison

    发明人： Monte Manning ,  Charles Dennison

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76

    CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

    摘要翻译： 本公开包括使用薄膜晶体管的优选半导体晶体管器件以及形成这种器件的优选方法。 具体地，形成具有顶表面的底部薄膜晶体管栅极。 在薄膜晶体管栅极附近提供绝缘填充物，至少与薄膜晶体管栅极顶表面一样高，并且随后平整以提供与薄膜晶体管栅极相邻的大致平面的绝缘表面。 平面绝缘表面基本上与薄膜晶体管栅极顶表面共面。 然后在薄膜晶体管栅极上方并在相邻的平面绝缘表面上形成平面半导体薄膜。 掺杂薄膜以形成薄膜晶体管的源区和漏极区，薄膜晶体管是由薄膜晶体管栅极选通的。

    Method for forming and tailoring the electrical characteristics of semiconductor devices
    54.
    发明授权
    Method for forming and tailoring the electrical characteristics of semiconductor devices 失效
    用于形成和定制半导体器件的电特性的方法

    公开(公告)号：US5661045A

    公开(公告)日：1997-08-26

    申请号：US763848

    申请日：1996-12-09

    申请人： Monte Manning ,  Charles Dennison ,  Howard Rhodes ,  Tyler Lowrey

    发明人： Monte Manning ,  Charles Dennison ,  Howard Rhodes ,  Tyler Lowrey

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8244 ,  H01L21/265

    CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L27/11

    摘要： A method for forming semiconductor devices includes a low energy implant for tailoring the electrical characteristics of the semiconductor devices. Using the low energy implant, narrow width devices such as access transistors in an SRAM cell, can be fabricated with a low threshold voltage (Vt). The low energy implant is performed on the active areas of a silicon substrate following field isolation and field implant. For an n-conductivity access transistor, the low energy dopant can be an n-type dopant such as phosphorus, arsenic or antimony.

    摘要翻译： 用于形成半导体器件的方法包括用于调整半导体器件的电特性的低能量注入。 使用低能量注入，可以以低阈值电压（Vt）制造诸如SRAM单元中的存取晶体管的窄宽度器件。 在场隔离和场植入之后，在硅衬底的有源区域上执行低能量注入。 对于n导电性存取晶体管，低能掺杂剂可以是n型掺杂剂，例如磷，砷或锑。

    Initializing phase change memories
    55.
    发明申请
    Initializing phase change memories 有权
    初始化相变记忆

    公开(公告)号：US20080116444A1

    公开(公告)日：2008-05-22

    申请号：US11998899

    申请日：2007-12-03

    申请人： Charles Dennison

    发明人： Charles Dennison

    IPC分类号： H01L47/00

    CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

    摘要： A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.

    摘要翻译： 薄膜相变存储器可以设置有在非晶态和晶态之间变化的层。 该层的阈值电压可以以各种方式增加。 作为门限增加的结果，可以将初始以设定或低电阻状态制造的电池转换成复位或高电阻状态。 在一个有利的实施例中，在这样的初始化和编程之后，消除阈值电压增加，使得在没有增加的阈值电压的情况下，电池工作。

    METHOD FOR AN INTEGRATED CIRCUIT CONTACT
    57.
    发明申请
    METHOD FOR AN INTEGRATED CIRCUIT CONTACT 失效
    集成电路联系方法

    公开(公告)号：US20070281487A1

    公开(公告)日：2007-12-06

    申请号：US11841906

    申请日：2007-08-20

    申请人： Charles Dennison ,  Trung Doan

    发明人： Charles Dennison ,  Trung Doan

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

    摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

    摘要翻译： 在集成电路和器件的制造中提供用于形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间可以重复上述过程。

    Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby
    59.
    发明授权
    Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby 有权
    选择性地去除相变存储单元的导电底电极的一侧的方法及由此得到的结构

    公开(公告)号：US07229887B2

    公开(公告)日：2007-06-12

    申请号：US10340506

    申请日：2003-01-10

    申请人： Charles Dennison

    发明人： Charles Dennison

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length that is less than the first side. Additionally, a second dielectric may overlie the lower electrode. The second dielectric has a shape that is substantially similar to the lower electrode.The present invention also relates to a method of making a phase-change memory device. The method includes providing a lower electrode material in a recess. The method also includes removing at least a portion of the second side.

    摘要翻译： 本发明涉及一种相变存储器件。 该装置包括设置在第一电介质的凹部中的下电极。 下电极包括第一侧和第二侧。 第一面与一定量的相变记忆材料通信。 第二面的长度小于第一面。 此外，第二电介质可以覆盖在下电极上。 第二电介质具有与下电极基本相似的形状。 本发明还涉及一种制造相变存储器件的方法。 该方法包括在凹部中提供下电极材料。 该方法还包括移除第二侧的至少一部分。