公开(公告)号：US07605018B2

公开(公告)日：2009-10-20

申请号：US12007008

申请日：2008-01-04

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L21/44

CPC分类号： H01L21/4867 ,  H01L21/481 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49833 ,  H01L24/27 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/8385 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a method for forming a die-attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. Top surface of the substrate core includes a plurality of die-attaching units and a peripheral area enclosed by the stiffener. A non-planar printing stencil is also provided. When the non-planar printing stencil is pressed against the chip carrier, the non-planar printing stencil is compliantly in contact with the substrate core and the stiffener and a plurality of printing openings of the non-planar printing stencil exposes the substrate core within the die-attaching units. During stencil printing, die-attach material fills in the printing openings to directly adhere to the substrate core. Therefore, the warpage of the substrate core is restrained to avoid bleeding of die-attach material so that die-attach materials can be formed as a die-attach layer with a uniform thickness on core-exposed chip carrier with lower costs. Additionally, the chip carrier will not be deformed during semiconductor packaging processes.

公开(公告)号：US20090224377A1

公开(公告)日：2009-09-10

申请号：US12044990

申请日：2008-03-09

申请人： Wen-Jeng Fan ,  Yu-Mei Hsu

发明人： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.

摘要翻译： 揭示了具有用于引线键合的线性锯齿形的半导体器件，主要包括芯片，由引线框架制成的多个引线和电连接芯片和引线的多个接合线。 引线中的至少一个具有包括以锯齿形形式彼此连接的第一手指和第二手指的线性之字形。 接合线中的一个的一端被接合到芯片上的接合焊盘，另一端选择性地接合到第一指状物或第二指状物上，但不是以使得接合线的引线键合方向为 与连接的手指的方向平行或成锐角，以便于引线接合过程。 因此，半导体器件可以通过线性锯齿形的柔性引线接合角度来组装具有不同尺寸的芯片或具有不同的焊盘布局，以避免相邻引线之间的电短路。

公开(公告)号：US20090160038A1

公开(公告)日：2009-06-25

申请号：US12068613

申请日：2008-02-08

申请人： Wen-Jeng Fan ,  Yu-Mei Hsu

发明人： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.

摘要翻译： LOC引线框架半导体封装包括具有多排焊盘的芯片。 至少一个母线连接在芯片上，并且设置在第一排接合焊盘和引线的指状物之间。 多个接合线将第一排接合焊盘电连接到引线的指状物。 汇流条附接到芯片的有效表面的部分包括弯曲部分，该弯曲部分远离手指弯曲。 长接合线通过超过弯曲部分将第二排接合焊盘中的一个电线连接到引线的一个指状物。 因此，长接合线和母线之间的距离增加，以避免长接合线和母线之间的电短路并且提高LOC半导体封装的电连接的质量。

公开(公告)号：US20080157334A1

公开(公告)日：2008-07-03

申请号：US11647376

申请日：2006-12-29

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  G11C5/04 ,  H01L23/13 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/181 ,  H05K2201/09063 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory module for improving impact resistance mainly comprises a multi-layer PWB (Printed Wiring Board) and a plurality of memory packages. The multi-layer PWB is rectangular and has two longer sides and two shorter sides, wherein a plurality of gold fingers are disposed along one of the longer sides, at least an arc notch and a plurality of first stress-absorbing slots are formed at the two shorter sides respectively. Preferably, plural second stress-absorbing slots are formed at another longer side far away from the gold fingers. The impact stress due to accidental drop may be absorbed by the first stress-absorbing slots or/and the second stress-absorbing slots to prevent the product from damaging.

摘要翻译： 用于改善抗冲击性的存储器模块主要包括多层PWB（印刷线路板）和多个存储器封装。 多层PWB是矩形的，具有两个长边和两个短边，其中多个金指沿着一个长边设置，至少一个弧形凹口和多个第一应力吸收槽形成在 两个短边分别。 优选地，多个第二应力吸收槽形成在远离金手指的另一较长侧。 由于意外跌落引起的冲击应力可能被第一应力吸收槽或/和第二应力吸收槽所吸收，以防产品损坏。

公开(公告)号：US20080142985A1

公开(公告)日：2008-06-19

申请号：US11640262

申请日：2006-12-18

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48

CPC分类号： H05K1/0271 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/28 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

摘要： A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of the core layer to cover the traces with the connecting pads partially or completely exposed. Furthermore, the traces have I-shaped cross sections to enhance the tensile strength of the traces.

摘要翻译： 具有拉伸强度增强迹线的布线基板主要包括芯层，多个连接焊盘，多个迹线和阻焊层，其中连接焊盘和迹线设置在芯层的顶部。 阻焊层形成在芯层的顶部上，以覆盖具有部分或完全暴露的连接焊盘的迹线。 此外，迹线具有I形横截面以增强迹线的拉伸强度。

公开(公告)号：US08053676B2

公开(公告)日：2011-11-08

申请号：US12191645

申请日：2008-08-14

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H05K1/03 ,  H05K7/00

CPC分类号： H05K3/242 ,  H05K3/0052 ,  H05K2201/09254

摘要： A substrate panel primarily comprises a plurality of substrate strips arranged in an array, one or more current input lines, a plurality of cascaded lines connecting between the substrate strips, and a current input buffer gate. Current input lines connect a current input side of the substrate panel to the adjacent substrate strips. The current input buffer gate has a frame around the substrate strips and a plurality of meshes where the frame intersects with the current input lines and the meshes intersect with the cascaded lines with both ends of the meshes connecting to the frame. Therefore, the current can be evenly distributed to each substrate strip during plating processes to improve the issues of different plating thicknesses and different plating roughness caused by different current densities and to protect the internal circuits inside the substrate strips from the damages due to current surges and unstable voltages.

摘要翻译： 衬底面板主要包括布置成阵列的多个衬底条，一个或多个电流输入线，连接在衬底条之间的多条级联线和电流输入缓冲门。 电流输入线将基板面板的电流输入侧连接到相邻的基板条。 当前输入缓冲器门具有围绕衬底条的框架以及框架与当前输入线相交的多个网格，并且网格与连接到框架的网格的两端的级联线相交。 因此，电镀过程中电流可以均匀地分布到每个衬底条上，以改善由不同电流密度引起的不同电镀厚度和不同电镀粗糙度的问题，并保护衬底条内部的电路免受由于电流浪涌引起的损坏， 电压不稳定

公开(公告)号：US07952168B2

公开(公告)日：2011-05-31

申请号：US12042086

申请日：2008-03-04

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/544

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L24/97 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A substrate strip for semiconductor packages to slow the crack growth, primarily comprises a molding area and two side rails. The molding area includes a plurality of packaging units. The side rails are located outside the molding area and include two opposing longer sides of the substrate strip. A metal mesh is disposed on the side rails. The metal mesh consists of a plurality of crisscrossed wires having a plurality of isolated wire terminals at one edge of the metal mesh. Accordingly, crack growth is slowed by the specific metal mesh without damaging the packaging units. In one embodiment, the metal mesh is without boundary wires connecting to the isolated wire terminals to enhance the resistance to crack growth.

摘要翻译： 用于半导体封装的用于减缓裂纹扩展的衬底条主要包括模制区和两个侧轨。 成型区域包括多个包装单元。 侧轨位于模制区域的外侧，并且包括衬底条的两个相对的较长边。 金属网布置在侧轨上。 金属网由在金属网的一个边缘处具有多个隔离的导线端子的多个十字交叉的导线组成。 因此，特定金属网的裂纹扩展减慢，而不损害包装单元。 在一个实施例中，金属网没有连接到隔离导线端子的边界线，以增强对裂纹扩展的抵抗力。

公开(公告)号：US07750444B2

公开(公告)日：2010-07-06

申请号：US12122946

申请日：2008-05-19

申请人： Wen-Jeng Fan ,  Yu-Mei Hsu

发明人： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads.

摘要翻译： 显示了具有封装引线框的LOC半导体封装。 LOC半导体封装主要包括多个引线框的引线，至少一个连接条，芯片和封装上述部件的密封剂。 每个引线都有一个粘结手指。 连接杆具有虚拟手指，其中虚拟手指线性地设置在接合指的配置区域的一侧。 该芯片具有带有接合指状物的活性表面。 当虚设手指和结合指状物通过管芯附着层设置在有效表面上方时，虚拟手指与活动表面的一个边缘相邻。 接合指状物与接合焊盘电连接。 虚拟手指将承受集中应力，以避免活动表面上的粘结指状物由于外部应力而分层或断裂，并避免对引线布局的干扰。

公开(公告)号：US20100122454A1

公开(公告)日：2010-05-20

申请号：US12274694

申请日：2008-11-20

申请人： Wen-Jeng Fan ,  Yu-Mei Hsu

发明人： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC分类号： H01R43/00

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method for forming an isolated inner lead from a leadframe is revealed. The leadframe primarily comprises a plurality of leads, the isolated inner lead, and an external lead. Each lead has an inner portion having a finger. The isolated inner lead having two fingers is completely formed inside a molding area and is made of the same metal leadframe as the leads. One finger of the isolated inner lead and the fingers of the leads are linearly arranged. The other finger of the isolated inner lead is adjacent to a finger of the external lead. At least one of the inner portions divides the isolated inner lead from the external lead. The isolated inner lead is integrally connected to an adjacent one of the inner portions by a connecting block. A tape-attaching step is performed to mechanically connect the isolated inner lead where two insulating tapes are attached in a manner that the connecting block can be removed. Therefore, the isolated inner lead is electrically isolated from the leads and can be mechanically fixed to replace extra redistributing components during semiconductor packaging processes.

摘要翻译： 揭示了从引线框形成隔离内引线的方法。 引线框架主要包括多个引线，隔离内引线和外引线。 每个引线具有具有手指的内部部分。 具有两个指状物的隔离内部引线在成型区域内完全形成，并且由与引线相同的金属引线框构成。 隔离的内引线和引线的指状物的一个指状物线性排列。 隔离的内引线的另一个手指与外引线的手指相邻。 内部部分中的至少一个将隔离的内部引线与外部引线分开。 隔离的内引线通过连接块一体连接到相邻的一个内部部分。 执行胶带附着步骤以将连接块移除的方式机械地连接隔离的内引线，其中两个绝缘带被附接。 因此，隔离的内部引线与引线电隔离，并且可以机械固定以在半导体封装工艺期间替换额外的再分配组件。

公开(公告)号：US07566963B2

公开(公告)日：2009-07-28

申请号：US11984771

申请日：2007-11-21

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/02

CPC分类号： H01L23/49541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.