公开(公告)号：US07050316B1

公开(公告)日：2006-05-23

申请号：US10797207

申请日：2004-03-09

申请人： Ya-Fen Lin ,  Elbert Lin ,  Dana Lee ,  Bomy Chen ,  Hung Q. Nguyen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Dana Lee ,  Bomy Chen ,  Hung Q. Nguyen

IPC分类号： G11C15/00

CPC分类号： G11C15/046 ,  G11C13/0004

摘要： A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line. A match line is connected to the first and second storage elements for indicating whether a match occurred between the first bit and the first stored bit, and between the second bit and the second stored bit

摘要翻译： 差分感测内容可寻址存储单元，没有连接到同一行中的单元的任何字线包括用于提供第一位的第一位线。 第一存储元件具有第一相变电阻器，用于存储与第一二极管串联连接的第一存储位。 第一存储元件连接到第一位线。 第二位线提供第二位，第二位是第一位的倒数。 第二存储元件具有用于存储与第二二极管串联连接的第二存储位的第二相变电阻器。 第二存储元件连接到第二位线。 匹配线连接到第一和第二存储元件，用于指示在第一位和第一存储位之间以及第二位和第二存储位之间是否发生匹配

公开(公告)号：US20060091449A1

公开(公告)日：2006-05-04

申请号：US11303567

申请日：2005-12-15

申请人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

发明人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。

公开(公告)号：US20050224861A1

公开(公告)日：2005-10-13

申请号：US10822944

申请日：2004-04-12

申请人： Dana Lee ,  Hieu Tran ,  Jack Frayer

发明人： Dana Lee ,  Hieu Tran ,  Jack Frayer

IPC分类号： H01L21/8247 ,  G11C16/04 ,  G11C16/14 ,  H01L21/28 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

摘要： An isolation-less, contact-less nonvolatile memory array has a plurality of memory cells each with a floating gate for the storage of charges thereon, arranged in a plurality of rows and columns. Each memory cell can be of a number of different types. All the bit lines and source lines of the various embodiments are buried and are contact-less. In a first embodiment, each cell can be represented by a stacked gate floating gate transistor coupled to a separate assist transistor. The entire array can be planar; or in a preferred embodiment each of the floating gate transistors is in a trench; or each of the assist transistors is in a trench. In a second embodiment, each cell can be represented by a stacked gate floating gate transistor with the transistor in a trench. In a third embodiment, each cell can be represented by two stacked gate floating gate transistors coupled to a separate assist transistor, positioned between the two stacked gate floating gate transistors. The entire array can be planar; or in a preferred embodiment each of the floating gate transistors is in a trench; or each of the assist transistors is in a trench. Novel methods to manufacture the arrays and methods to program, erase, and read each of these embodiments of the memory cells is disclosed.

摘要翻译： 无隔离的非接触式非易失性存储器阵列具有多个存储单元，每个存储单元具有用于在其上存储电荷的浮动栅极，其布置成多个行和列。 每个存储单元可以是多种不同的类型。 各种实施例的所有位线和源极线被掩埋并且是无接触的。 在第一实施例中，每个单元可以由耦合到单独的辅助晶体管的堆叠栅极浮栅晶体管表示。 整个阵列可以是平面的; 或者在优选实施例中，每个浮栅晶体管处于沟槽中; 或者每个辅助晶体管处于沟槽中。 在第二实施例中，每个单元可以由晶体管在沟槽中的层叠栅极浮栅晶体管表示。 在第三实施例中，每个单元可以由耦合到位于两个堆叠的栅极浮置栅极晶体管之间的单独的辅助晶体管的两个堆叠的栅极浮栅晶体管表示。 整个阵列可以是平面的; 或者在优选实施例中，每个浮栅晶体管处于沟槽中; 或者每个辅助晶体管处于沟槽中。 公开了制造阵列的新方法和编程，擦除和读取存储器单元的这些实施例的每一个的方法。

公开(公告)号：US06913975B2

公开(公告)日：2005-07-05

申请号：US10885923

申请日：2004-07-06

申请人： Bomy Chen ,  Dana Lee ,  Bing Yeh

发明人： Bomy Chen ,  Dana Lee ,  Bing Yeh

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66825

摘要： A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. A bi-directional non-volatile memory cell has two floating gates each formed in a cavity. A method of making the non-volatile memory cell and the array are also disclosed.

摘要翻译： 非易失性存储单元具有第一导电类型的单结晶硅单晶硅。 在半导体材料中形成有彼此间隔开的与第一导电类型不同的第二导电类型的第一和第二区域。 具有第一部分的通道区域和第二部分连接用于电荷传导的第一和第二区域。 电介质在沟道区上。 可以是导电或非导电的浮动栅极位于电介质上，与沟道区的第一部分间隔开。 沟道区域的第一部分与第一区域相邻，第一浮栅具有大致三角形形状。 浮动门形成在空腔中。 栅极电极电容耦合到第一浮动栅极，并且与沟道区域的第二部分间隔开。 沟道区域的第二部分在第一部分和第二区域之间。 双向非易失性存储单元具有分别形成在空腔中的两个浮动栅极。 还公开了制造非易失性存储单元和阵列的方法。

公开(公告)号：US06906379B2

公开(公告)日：2005-06-14

申请号：US10653015

申请日：2003-08-28

申请人： Bomy Chen ,  Dana Lee ,  Hieu Van Tran

发明人： Bomy Chen ,  Dana Lee ,  Hieu Van Tran

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

摘要： An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

摘要翻译： 一种浮动栅极存储单元的阵列及其制造方法，其中每对存储单元包括形成在半导体衬底的表面中的一对沟槽，其中衬底的条带设置在其间，源区域形成在 衬底条，一对漏极区，一对沟道区，每个沟道区各自在源极区和漏极区之一之间延伸;一对浮置栅极，分别设置在一个沟槽中，以及一对控制栅极。 每个通道区域具有设置在衬底条中并沿​​其中一个沟槽延伸的第一部分，在一个沟槽下面延伸的第二部分，沿该沟槽延伸的第三部分，以及沿衬底表面延伸的第四部分 的控制门。

公开(公告)号：US06593177B2

公开(公告)日：2003-07-15

申请号：US09972179

申请日：2001-10-05

申请人： Dana Lee

发明人： Dana Lee

IPC分类号： H01L2964

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates. A bit line is formed in the bit line direction contacting the second region in the space between the control gates.

公开(公告)号：US06525371B2

公开(公告)日：2003-02-25

申请号：US09401622

申请日：1999-09-22

申请人： Jeffrey B. Johnson ,  Chung H. Lam ,  Dana Lee ,  Dale W. Martin ,  Jed H. Rankin

发明人： Jeffrey B. Johnson ,  Chung H. Lam ,  Dana Lee ,  Dale W. Martin ,  Jed H. Rankin

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates. A bit line is formed in the bit line direction contacting the second region in the space between the control gates.

摘要翻译： 在半导体衬底中形成浮动栅极存储单元的半导体存储器阵列的自对准方法在基板上具有基本上彼此平行的多个间隔开的隔离区域。 有源区域位于每对相邻隔离区域之间。 活性隔离区域和平行区域形成为平行且在列方向。 在行方向上，形成间隔开的氮化硅的条。 源极线插塞形成在相邻的氮化硅对之间并且与有源区域中的第一区域以及隔离区域接触。 去除氮化硅条并进行各向同性蚀刻。 此外，氮化硅下方的材料也被各向同性地蚀刻。 然后在平行于源极线插塞并与浮动栅极相邻的行方向上形成多晶硅间隔物，以形成连接的控制栅极。 第二区域形成在相邻的间隔开的控制门之间。 在与控制栅极之间的空间中的第二区域接触的位线方向上形成位线。

公开(公告)号：US09430322B2

公开(公告)日：2016-08-30

申请号：US13565650

申请日：2012-08-02

申请人： Jonathan Wolfman ,  Dana Lee ,  Jonathan Hsu

发明人： Jonathan Wolfman ,  Dana Lee ,  Jonathan Hsu

IPC分类号： G06F12/02 ,  G06F11/10 ,  H04L1/00 ,  G06F11/30 ,  G01R31/317 ,  G06F12/06 ,  G11C16/04 ,  G06F11/07 ,  G06F12/16 ,  G11C16/34 ,  G11C29/04

CPC分类号： G06F11/1048 ,  G01R31/3171 ,  G06F11/07 ,  G06F11/076 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/16 ,  G06F2212/7211 ,  G11C16/04 ,  G11C16/34 ,  G11C16/349 ,  G11C2029/0409 ,  H04L1/0061

摘要： A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.

摘要翻译： 可以使用用于改善基于固有耐力的块的管理和使用的系统来改善诸如存储卡的闪存的存储器使用。 整体卡耐力可以通过在最差块的最低耐力目标下具有较高内在耐力的循环块来延长。 这可以通过内部管理具有不同内在耐力值的块来实现，或者通过外部对不同的内在耐力值进行分区，以实现不同的使用。

公开(公告)号：US09152497B2

公开(公告)日：2015-10-06

申请号：US13974997

申请日：2013-08-23

申请人： Dana Lee ,  Abhijeet Manohar

发明人： Dana Lee ,  Abhijeet Manohar

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C16/34 ,  G11C29/50 ,  G11C29/04

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C16/3431 ,  G11C29/00 ,  G11C29/50004 ,  G11C29/50008 ,  G11C2029/0411 ,  G11C2029/5002

摘要： A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.

摘要翻译： 存储模块可以包括NAND型闪存阵列和一个或多个控制器，其被配置为增加施加到存储器阵列中的栅极的栅极偏置电压电平，以克服可能的栅极短路并恢复被识别为不可校正的数据。 增加的栅极偏置电压可以施加到单个晶体管的栅极或存储器阵列中的不同类型的晶体管，包括漏极选择晶体管，源极选择晶体管或浮动栅极晶体管。

公开(公告)号：US09053808B2

公开(公告)日：2015-06-09

申请号：US13529522

申请日：2012-06-21

申请人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

发明人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

IPC分类号： G06F11/00 ,  G11C16/34 ,  G11B20/18

CPC分类号： G11C16/3418 ,  G11B20/18 ,  G11B20/1883 ,  G11C16/3427 ,  G11C16/3431

摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.

摘要翻译： 已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。 该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。 控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。 然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。 块刷新过程可以包括在后台操作期间将数据从块复制到新块中。