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    Self-aligned non-volatile random access memory cell and process to make the same
    1.
    发明授权
    Self-aligned non-volatile random access memory cell and process to make the same 有权
    自对准非易失性随机存取存储器单元和过程相同

    公开(公告)号：US06525371B2

    公开(公告)日：2003-02-25

    申请号：US09401622

    申请日：1999-09-22

    申请人： Jeffrey B. Johnson ,  Chung H. Lam ,  Dana Lee ,  Dale W. Martin ,  Jed H. Rankin

    发明人： Jeffrey B. Johnson ,  Chung H. Lam ,  Dana Lee ,  Dale W. Martin ,  Jed H. Rankin

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

    摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates. A bit line is formed in the bit line direction contacting the second region in the space between the control gates.

    摘要翻译： 在半导体衬底中形成浮动栅极存储单元的半导体存储器阵列的自对准方法在基板上具有基本上彼此平行的多个间隔开的隔离区域。 有源区域位于每对相邻隔离区域之间。 活性隔离区域和平行区域形成为平行且在列方向。 在行方向上，形成间隔开的氮化硅的条。 源极线插塞形成在相邻的氮化硅对之间并且与有源区域中的第一区域以及隔离区域接触。 去除氮化硅条并进行各向同性蚀刻。 此外，氮化硅下方的材料也被各向同性地蚀刻。 然后在平行于源极线插塞并与浮动栅极相邻的行方向上形成多晶硅间隔物，以形成连接的控制栅极。 第二区域形成在相邻的间隔开的控制门之间。 在与控制栅极之间的空间中的第二区域接触的位线方向上形成位线。

    Isolated fully depleted silicon-on-insulator regions by selective etch
    5.
    发明授权
    Isolated fully depleted silicon-on-insulator regions by selective etch 失效
    通过选择性蚀刻隔离完全耗尽的绝缘体上硅区域

    公开(公告)号：US07190007B2

    公开(公告)日：2007-03-13

    申请号：US10710821

    申请日：2004-08-05

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

    IPC分类号： H01L29/47

    CPC分类号： H01L21/764 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/78654

    摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

    摘要翻译： 本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。 半导体区域的上部含Si表面具有小于约的均匀厚度。

    Method of forming a point on a floating gate for electron injection
    6.
    发明授权
    Method of forming a point on a floating gate for electron injection 失效
    在浮栅上形成电子注入点的方法

    公开(公告)号：US06294429B1

    公开(公告)日：2001-09-25

    申请号：US09448157

    申请日：1999-11-24

    申请人： Chung H. Lam ,  Dale W. Martin ,  Christa R. Willets

    发明人： Chung H. Lam ,  Dale W. Martin ,  Christa R. Willets

    IPC分类号： H01L21336

    CPC分类号： H01L29/66583 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/28273 ,  H01L29/42368 ,  H01L29/42376

    摘要： The present invention relates to a method of forming a charge injection region on a floating gate of a memory cell using an etching process. The present invention defines the sharp corners for electron charge injection region of a floating gate by etching the shape into the floating gate silicon rather than forming the injection point using an oxidation process. By using the etching process of the present invention, limitations on the size of the floating gate are overcome and the memory cell can be formed using the minimum geometry allowed by lithography. This allows further scaling of the cell film thickness than is presently capable and does not limit the choice of insulator film materials.

    摘要翻译： 本发明涉及使用蚀刻工艺在存储单元的浮动栅极上形成电荷注入区域的方法。 本发明通过将形状蚀刻到浮动栅极硅中而不是使用氧化工艺形成注入点来限定浮动栅极的电子电荷注入区域的尖角。 通过使用本发明的蚀刻工艺，克服了对浮栅的尺寸的限制，并且可以使用光刻所允许的最小几何形状来形成存储单元。 这允许细胞膜厚度比当前能够进一步缩放，并且不限制绝缘膜材料的选择。

    Gate stacks
    7.
    发明授权
    Gate stacks 有权
    门堆叠

    公开(公告)号：US07378712B2

    公开(公告)日：2008-05-27

    申请号：US11463039

    申请日：2006-08-08

    申请人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    发明人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

    摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

    摘要翻译： 门堆栈结构。 该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。 栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域 并掺杂一种掺杂剂。 该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。 扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止 含氧材料通过扩散阻挡区扩散。

    Method for providing multiple gate oxide thicknesses on the same wafer
    8.
    发明授权
    Method for providing multiple gate oxide thicknesses on the same wafer 失效
    在同一晶片上提供多个栅极氧化物厚度的方法

    公开(公告)号：US5926708A

    公开(公告)日：1999-07-20

    申请号：US859588

    申请日：1997-05-20

    申请人： Dale W. Martin

    发明人： Dale W. Martin

    IPC分类号： H01L21/8234 ,  H01L21/8242

    CPC分类号： H01L21/823462

    摘要： The present invention is directed to a method of manufacturing an integrated circuit with two or more gate oxide thicknesses on the same wafer. The method includes the steps of growing a first oxide layer on a substrate, depositing a first polysilicon layer over the first oxide layer, applying a block mask, etching the first polysilicon layer, stripping the block mask, stripping the first oxide layer from the areas opened by the block mask, growing a second oxide layer, depositing a second polysilicon layer, and polishing the second polysilicon layer to remove the second polysilicon layer from everywhere except the areas opened by the block mask. If desired, a polish stop layer may be deposited after depositing the first polysilicon layer. Threshold implants may also be made after the block mask is stripped. Finally, polysilicon shapes may be added to the boundary areas opened by the block mask to help eliminate foreign material problems.

    摘要翻译： 本发明涉及在同一晶片上制造具有两个或多个栅极氧化物厚度的集成电路的方法。 该方法包括以下步骤：在衬底上生长第一氧化物层，在第一氧化物层上沉积第一多晶硅层，施加阻挡掩模，蚀刻第一多晶硅层，剥离阻挡掩模，从区域剥离第一氧化物层 通过块掩模打开，生长第二氧化物层，沉积第二多晶硅层，以及抛光第二多晶硅层以除去由阻挡掩模打开的区域以外的任何地方的第二多晶硅层。 如果需要，可以在沉积第一多晶硅层之后沉积抛光停止层。 剥离块掩模后也可以进行阈值植入。 最后，可以将多晶硅形状添加到通过阻挡掩模打开的边界区域，以帮助消除异物问题。

    Gate stacks
    10.
    发明授权
    Gate stacks 失效
    门堆叠

    公开(公告)号：US07157341B2

    公开(公告)日：2007-01-02

    申请号：US10711742

    申请日：2004-10-01

    申请人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    发明人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

    摘要： A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.

    摘要翻译： 用于限定半导体衬底中的源极/漏极区域的栅堆叠的结构和制造方法。 该方法包括：（a）在衬底的顶部形成栅介质层，（b）在栅极介电层的顶部形成栅极多晶硅层，（c）在栅极多晶硅层的顶层中注入n型掺杂剂 ，（d）蚀刻掉栅极多晶硅层和栅极电介质层的部分，以在衬底上形成栅极堆叠，以及（e）在存在氮气的气体下热氧化栅极堆叠的侧壁。 结果，无论掺杂浓度如何，在栅叠层的多晶硅材料中，在相同的深度处形成扩散阻挡层。 因此，栅极堆叠的n型掺杂区域具有与栅极堆叠的未掺杂区域相同的宽度。