公开(公告)号：US5003459A

公开(公告)日：1991-03-26

申请号：US176595

申请日：1988-04-01

申请人： Raj K. Ramanujan ,  Simon C. Steely, Jr. ,  Peter J. Bannon ,  David J. Sager

发明人： Raj K. Ramanujan ,  Simon C. Steely, Jr. ,  Peter J. Bannon ,  David J. Sager

IPC分类号： G06F12/10

CPC分类号： G06F12/1045

摘要： The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.

摘要翻译： 本发明涉及包括虚拟高速缓冲存储器，物理高速缓冲存储器，虚拟到物理转换缓冲器，物理到虚拟背景图，旧PA指针和锁定寄存器的数据处理器中的高速缓冲存储器系统。 反向映射通过清除虚拟高速缓存中的有效标志来实现无效。 Old-PA指针指示在虚拟缓存中的引用未命中之后，将无效的背景条目。 写入虚拟高速缓冲存储器的数据的物理地址由转换缓冲区输入到旧PA指针。 锁定寄存器阻止对虚拟高速缓冲存储器中可能具有同义词的数据的所有引用。 背景图也用于使任何同义词无效。

公开(公告)号：US20110208918A1

公开(公告)日：2011-08-25

申请号：US12978513

申请日：2010-12-24

申请人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

发明人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/384 ,  Y02D10/13

摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

摘要翻译： 描述与硬件移动消除和/或下一页预取相关的方法和装置。 在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。 在一个实施例中，公开了下一页预取器。 还描述和要求保护其他实施例。

公开(公告)号：US07100012B2

公开(公告)日：2006-08-29

申请号：US10629244

申请日：2003-07-28

申请人： David J. Sager

发明人： David J. Sager

IPC分类号： G06F13/00 ,  G06F1/04

CPC分类号： G06F12/0893 ,  G06F9/383 ,  G06F9/3863

摘要： A processor includes a cache memory with a data storage unit operating at a first clock frequency, and a tag unit and hit/miss logic operating at a second clock frequency different than the first clock frequency. The data storage unit may advantageously be clocked faster than the tag unit and hit/miss logic, such as two times (2×) faster. The processor may also include a replay mechanism for recovering from data speculation when the hit/miss logic or the tag unit signals that speculated data from the higher clocked data storage unit is, in fact, invalid.

公开(公告)号：US06928647B2

公开(公告)日：2005-08-09

申请号：US10365918

申请日：2003-02-13

申请人： David J. Sager

发明人： David J. Sager

IPC分类号： G06F9/48 ,  G06F15/16

CPC分类号： G06F9/4831 ,  G06F9/4881

摘要： The present invention provides a method and apparatus for controlling a processing priority assigned alternately to a first thread and a second thread in a multithreaded processor to prevent deadlock and livelock problems between the first thread and the second thread. In one embodiment, the processing priority is initially assigned to the first thread for a first duration. It is then determined whether the first duration has expired in a given processing cycle. If the first duration has expired, the processing priority is assigned to the second thread for a second duration.

摘要翻译： 本发明提供一种方法和装置，用于控制在多线程处理器中交替地分配给第一线程和第二线程的处理优先级，以防止第一线程和第二线程之间的死锁和动态锁定问题。 在一个实施例中，处理优先级最初在第一持续时间内被分配给第一线程。 然后在给定的处理周期中确定第一持续时间是否已经过期。 如果第一持续时间已经过期，则处理优先级被分配给第二个线程持续第二个持续时间。

公开(公告)号：US06704861B1

公开(公告)日：2004-03-09

申请号：US08752729

申请日：1996-11-19

申请人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

发明人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

IPC分类号： G06F938

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/3865

摘要： A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.

摘要翻译： 用于并行执行计算机指令的机构包括：编译器，用于将指令生成和分组成并行执行的多组指令，每组具有唯一的标识。 具有实际状态和推测状态的计算机系统并行地执行集合，如果特定集合的指令具有在实际执行指令之前无法解析的依赖关系，则计算机系统在推测状态下执行特定指令集 。 计算机系统在推测状态下执行指令时生成推测数据。 提供逻辑电路以检测在推测状态下执行特定集合时发生的任何异常情况。 如果特定集合受到异常条件的影响，则重新执行该集合的指令以解决异常条件，并将推测数据并入计算机系统的实际状态。

公开(公告)号：US5966544A

公开(公告)日：1999-10-12

申请号：US746547

申请日：1996-11-13

申请人： David J. Sager

发明人： David J. Sager

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3838 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3869

摘要： A microprocessor having a replay architecture with an execution core for performing data speculation in executing an instruction, a delay unit for making a copy of the instruction and holding the copy for as long as the instruction takes to execute, and a checker for determining whether the data speculation was bogus. If the data speculation was bogus, the delay unit and its buffer send the copy of the instruction back to the execution core for re-execution. A multiplexor coupled to the input of the execution core selects for execution among original instructions from the instruction cache, replay instructions from the delay unit, and manufactured instructions from various other units such as the TLB or tag units, according to a priority scheme.

摘要翻译： 一种具有执行核心的重放架构的微处理器，用于在执行指令时进行数据推测，延迟单元用于制作指令的副本并保持该指令执行的时间长度;以及检查器，用于确定是否 数据猜测是假的。 如果数据推测是假的，则延迟单元及其缓冲区将指令的副本发送回执行核心以重新执行。 耦合到执行核心的输入端的多路复用器根据优先级方案选择来自指令高速缓存的原始指令，来自延迟单元的重放指令和来自诸如TLB或标签单元的各种其他单元的制造指令的执行。

公开(公告)号：US5359630A

公开(公告)日：1994-10-25

申请号：US929623

申请日：1992-08-13

申请人： Paul C. Wade ,  David J. Sager ,  Andrey Varpahovsky

发明人： Paul C. Wade ,  David J. Sager ,  Andrey Varpahovsky

IPC分类号： G06F1/10 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04

CPC分类号： G06F1/10 ,  H04L7/0012 ,  H04L7/0338

摘要： A method and device for receiving data in a synchronous communication system. Data can be accurately transferred between two subsystems in a synchronous system even where the clock skew and propagation delay between the two subsystems is unlimited. The receiving subsystem is initialized to ensure synchronous data transfer over a theoretically infinite range. The transmitting subsystem transmits data and a forwarded clock to the receiving subsystem. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the clock of the receiving subsystem by controlling a multiplexer which selects the proper state device output to pass to another state device for alignment to the receiving subsystem's clock. The multiplexer is controlled by a circuit which monitors the capturing of the incoming data and determines the correct state device output to select for proper data alignment.

摘要翻译： 一种用于在同步通信系统中接收数据的方法和装置。 即使在两个子系统之间的时钟偏移和传播延迟是无限制的情况下，也可以在同步系统中的两个子系统之间精确地传输数据。 接收子系统被初始化以确保在理论上无限范围内的同步数据传输。 发送子系统向接收子系统发送数据和转发时钟。 在并行布置的三个状态设备中捕获数据，以消除最小延迟要求并扩展数据有效时间。 捕获的数据然后通过控制多路复用器对准接收子系统的时钟，多路复用器选择适当的状态设备输出传递到另一个状态设备以与接收子系统的时钟对准。 多路复用器由监视输入数据的捕获的电路控制，并确定正确的状态设备输出以选择正确的数据对准。

公开(公告)号：US4825412A

公开(公告)日：1989-04-25

申请号：US176448

申请日：1988-04-01

申请人： David J. Sager ,  Raj K. Ramanujan ,  Jeffrey L. Bell

发明人： David J. Sager ,  Raj K. Ramanujan ,  Jeffrey L. Bell

IPC分类号： G06F12/10 ,  G11C15/00

CPC分类号： G06F12/1045

摘要： A cache memory system in a data processor that has a main memory and a processing unit, the cache memory system including a virtually addressed storage cache. This virtually addressed storage cache is connected to the main memory for storing in storage cache locations preselected portions of data from the main memory. Each cache location includes a valid indicator to indicate the data in the cache location is current. A translation buffers is coupled to the storage cache, and translates a virtual address to a physical address. The backmap is coupled to the storage cache and the translation buffer, and invalidates data in the storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated. The cache memory system includes at least one lockout register for storing addresses for data which may exist in more than one storage location. The backmap invalidates all copies of the data in the storage cache after every reference to data in the storage cache using an address in the lockout register.

摘要翻译： 具有主存储器和处理单元的数据处理器中的高速缓冲存储器系统，所述高速缓存存储器系统包括虚拟地寻址的存储高速缓存。 该虚拟寻址的存储高速缓存连接到主存储器，用于存储来自主存储器的数据的预选部分的存储缓存位置。 每个高速缓存位置包括一个有效的指示符，以指示高速缓存位置中的数据是当前的。 翻译缓冲器耦合到存储高速缓存，并将虚拟地址转换为物理地址。 背景图被耦合到存储高速缓存和翻译缓冲器，并且通过仅在存储高速缓存中的数据被无效时，才通过生成有效指示符被清除的高速缓存位置的无效索引来使存储高速缓存中的数据无效。 高速缓冲存储器系统包括至少一个锁定寄存器，用于存储可能存在于多于一个存储位置的数据的地址。 每次使用锁定寄存器中的地址对存储缓存中的数据进行引用之后，后台映射将使存储缓存中的所有数据副本无效。

公开(公告)号：US4811364A

公开(公告)日：1989-03-07

申请号：US176570

申请日：1988-04-01

申请人： David J. Sager ,  Leon D. Hesch ,  Andrew D. Ingraham ,  William A. Samaras

发明人： David J. Sager ,  Leon D. Hesch ,  Andrew D. Ingraham ,  William A. Samaras

IPC分类号： G06F13/42 ,  G06F1/10 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04 ,  H04L25/02 ,  H04L25/14 ,  G06F11/00

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H04L25/14 ,  H04L7/02 ,  H04L7/0338

摘要： Data can be accurately transmitted between two subsystems even if the clock skew between the two subsystems is larger than one clock cycle by the method of the invention. In one embodiment data is loaded into N state devices in the sending subsystem while the receiver recovers data from the sending state devices in rotation with an N input multiplexer. Another embodiment forwards a clock signal from the sending subsystem along with a data vector of N state signals for recovery by a pair of state devices capturing data on the rising and falling edges of the forwarded clock. A further embodiment achieves double bandwidth by forwarding two clock signals.

摘要翻译： 即使通过本发明的方法两个子系统之间的时钟偏差大于一个时钟周期，也可以在两个子系统之间精确地传输数据。 在一个实施例中，数据被加载到发送子系统中的N个状态设备中，同时接收机利用N输入多路复用器从发送状态设备中旋转数据。 另一实施例将来自发送子系统的时钟信号与N个状态信号的数据向量一起转发，以便通过在转发的时钟的上升沿和下降沿捕获数据的一对状态设备进行恢复。 另一实施例通过转发两个时钟信号实现双倍带宽。

公开(公告)号：US09189233B2

公开(公告)日：2015-11-17

申请号：US13533821

申请日：2012-06-26

申请人： Ruchira Sasanka ,  Abhinav Das ,  Jeffrey J. Cook ,  Jayaram Bobba ,  Arvind Krishnaswamy ,  David J. Sager ,  Suresh Srinivas

发明人： Ruchira Sasanka ,  Abhinav Das ,  Jeffrey J. Cook ,  Jayaram Bobba ,  Arvind Krishnaswamy ,  David J. Sager ,  Suresh Srinivas

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F11/36 ,  G06F9/38 ,  G06F9/54 ,  G06F9/45

CPC分类号： G06F11/3612 ,  G06F8/456 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/54 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2213/0038

摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.

摘要翻译： 描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。 例如，根据一个实施例的方法包括：分析执行程序代码的单线程区域，所述分析包括识别所述单线程区域内的依赖性; 确定可以基于分析并行执行执行程序代码的单线程区域的部分; 将所述部分分配给两个或更多个并行执行轨道; 并且在分配的执行轨道上并行地执行这些部分。