公开(公告)号：US20120261672A1

公开(公告)日：2012-10-18

申请号：US13084594

申请日：2011-04-12

申请人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

发明人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

IPC分类号： H01L27/092 ,  H01L21/782 ,  H01L21/8238 ,  H01L27/12

CPC分类号： H01L21/823814 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84

摘要： A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

摘要翻译： 公开了用于形成用于互补金属氧化物半导体场效应晶体管（CMOS晶体管）的电介质间隔物和外延层的半导体结构和方法。 具体地，该结构和方法包括形成设置在沟槽中并且与硅衬底相邻的电介质间隔物，这使漏电流最小化。 此外，沉积外延层以形成源极和漏极区域，其中源极区域和漏极区域彼此间隔一定距离。 外延层邻近电介质间隔物和晶体管本体区域（即，栅极下方的衬底部分）设置，这可使晶体管结电容最小化。 最小化晶体管结电容可以提高CMOS晶体管的开关速度。 因此，应用介电间隔物和外延层以最小化CMOS晶体管中的漏电流和晶体管结电容可以增强低功率应用中CMOS晶体管的效用和性能。

公开(公告)号：US08176444B2

公开(公告)日：2012-05-08

申请号：US12426475

申请日：2009-04-20

申请人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

发明人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10

摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

摘要翻译： 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US08168489B2

公开(公告)日：2012-05-01

申请号：US11782429

申请日：2007-07-24

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：US08119472B2

公开(公告)日：2012-02-21

申请号：US11757883

申请日：2007-06-04

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

IPC分类号： H01L21/8238

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

公开(公告)号：US08013397B2

公开(公告)日：2011-09-06

申请号：US12049450

申请日：2008-03-17

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L27/00

CPC分类号： H01L21/823807 ,  H01L21/28247 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.

摘要翻译： 本发明提供了一种半导体器件，其包括位于衬底的台面部分上的栅极区域; 以及位于所述栅极区域上的氮化物衬垫和与所述栅极区域相邻的所述衬底的凹陷表面，所述氮化物衬垫向所述栅极区域下方的器件沟道施加压力。 在器件通道上产生的应力是大约275MPa至大约450MPa的纵向应力。

公开(公告)号：US07989233B2

公开(公告)日：2011-08-02

申请号：US13004340

申请日：2011-01-11

申请人： Lidija Sekaric ,  Dureseti Chidambarrao ,  Xiao H. Liu

发明人： Lidija Sekaric ,  Dureseti Chidambarrao ,  Xiao H. Liu

IPC分类号： H01L29/06

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/7843 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

公开(公告)号：US07776695B2

公开(公告)日：2010-08-17

申请号：US11306716

申请日：2006-01-09

申请人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

发明人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

公开(公告)号：US20090177448A1

公开(公告)日：2009-07-09

申请号：US11970990

申请日：2008-01-08

申请人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

发明人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature.

摘要翻译： 一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层 衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。 该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化 由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。 根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。 然后，晶体管紧凑型模型中的晶体管模型参数值被更新为晶体管器件，以包括要添加到内置deltaW值的ΔW加法器值。 在设备仿真中使用的网表可以包括deltaW加法器值，以量化着陆垫特征的光刻舍入效应的影响。

公开(公告)号：US20090079011A1

公开(公告)日：2009-03-26

申请号：US12328358

申请日：2008-12-04

申请人： Dureseti Chidambarrao ,  Brian J. Greene

发明人： Dureseti Chidambarrao ,  Brian J. Greene

IPC分类号： H01L27/088 ,  H01L21/311

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/7842 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.

摘要翻译： 提供了克服双应力衬垫边界问题的方法和半导体结构，而不显着增加集成电路的总体尺寸。 根据本发明，它们之间的双应力衬垫边界或间隙被迫在邻近的虚拟栅极区域上着陆。 通过迫使衬垫之间的双重应力衬垫边界或间隙落在虚拟栅极区上，与双应力衬垫边界或间隙相关联的大应力被传递到虚拟栅极区而不是半导体衬底。 因此，双应力衬垫边界对最近的相邻FET的影响减小。 此外，利用本发明实现了装置可变性和包装密度的益处。

公开(公告)号：US20080283918A1

公开(公告)日：2008-11-20

申请号：US12166285

申请日：2008-07-01

申请人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Joseph Greene ,  Jack A. Mandelman ,  Kern Rim

发明人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Joseph Greene ,  Jack A. Mandelman ,  Kern Rim

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/3003 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78696

摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。 源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX 1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。 在UT通道区域下面的BOX 2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于 第二个深度。