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    Semiconductor memory device having synchronous write driver circuit
    51.
    发明授权
    Semiconductor memory device having synchronous write driver circuit 失效
    具有同步写入驱动电路的半导体存储器件

    公开(公告)号：US5841730A

    公开(公告)日：1998-11-24

    申请号：US790907

    申请日：1997-01-29

    申请人： Yasuyuki Kai ,  Katsushi Nagaba ,  Shigeo Ohshima

    发明人： Yasuyuki Kai ,  Katsushi Nagaba ,  Shigeo Ohshima

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/1048 ,  G11C7/1078

    摘要： A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array having a plurality of dynamic memory cells, to which data can be written, data line pairs to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.

    摘要翻译： 一种半导体存储器件，其能够在模式已经从写入模式改变为读取模式之后在第一读取周期中缩短数据读取时间，同时在尽可能简单的结构写入数据时保持高速循环时间，半导体存储器件具有 存储单元阵列，具有可以写入数据的多个动态存储器单元，从存储单元读取数据的数据线对和必须写入存储单元的数据被传送到其上，用于驱动数据线的写入驱动器 当数据被写入存储单元时，根据从外部提供的写入数据成对，以及均衡电路，用于每当数据线对由写入驱动器操作时将数据线对设置为中间电位。

    Multiport memory
    53.
    发明授权
    Multiport memory 失效
    多端口内存

    公开(公告)号：US5138581A

    公开(公告)日：1992-08-11

    申请号：US577361

    申请日：1990-09-05

    申请人： Shinji Miyamoto ,  Shigeo Ohshima

    发明人： Shinji Miyamoto ,  Shigeo Ohshima

    IPC分类号： G11C11/401 ,  G11C7/10

    CPC分类号： G11C7/1075

    摘要： A multiport memory has a RAM port including a memory cell array having a plurality of memory cells arranged in a matrix form, sense amplifier circuit for sensing potential of a bit line after the storage potential has been transferred from the memory cells, restore circuit connected to the bit line for pulling up the potential of the bit line at the predetermined timing after sense operation has been started and a barrier circuit connected between the bit line and the sense amplifier circuit; and a SAM port including a data register, transfer gate and functional means for transferring serial data in the column direction. In this memory, the RAM port is connected to the SAM port by the transfer gate with the bit line directly connected to the data register, and the potentials at the bit line are amplified by the sense amplifier circuit and are directly transferred to the data register.

    摘要翻译： 多端口存储器具有包括具有以矩阵形式布置的多个存储单元的存储单元阵列的RAM端口，用于在从存储单元传送存储电位之后感测位线的电位的读出放大器电路，恢复电路连接到 用于在感测操作之后的预定定时提升位线的电位的位线和连接在位线和读出放大器电路之间的屏障电路; 以及包括数据寄存器，传送门和用于在列方向上传送串行数据的功能装置的SAM端口。 在该存储器中，RAM端口通过传输门连接到SAM端口，位线直接连接到数据寄存器，位线上的电位由读出放大器电路放大并直接传输到数据寄存器 。

    Semiconductor memory system
    54.
    发明授权
    Semiconductor memory system 失效
    半导体存储系统

    公开(公告)号：US5107464A

    公开(公告)日：1992-04-21

    申请号：US480902

    申请日：1990-02-16

    申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/846

    摘要： In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.

    Flip-flop circuit
    56.
    发明授权
    Flip-flop circuit 失效
    触发电路

    公开(公告)号：US4678934A

    公开(公告)日：1987-07-07

    申请号：US884629

    申请日：1986-07-11

    申请人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    发明人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    IPC分类号： G11C11/40 ,  G11C8/06 ,  H03K3/356 ,  H03K3/26 ,  G11C7/00 ,  H03K17/687 ,  H03K19/094

    CPC分类号： H03K3/356026 ,  G11C8/06

    摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

    摘要翻译： 触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电， 与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

    METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE
    59.
    发明申请
    METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE 有权
    编程非易失性存储器件的方法

    公开(公告)号：US20080291716A1

    公开(公告)日：2008-11-27

    申请号：US12123827

    申请日：2008-05-20

    申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    IPC分类号： G11C11/00

    CPC分类号： G11C11/36

    摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

    摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

    Synchronous semiconductor memory
    60.
    发明授权
    Synchronous semiconductor memory 失效

    公开(公告)号：US07120078B2

    公开(公告)日：2006-10-10

    申请号：US10948818

    申请日：2004-09-23

    申请人： Kazuaki Kawaguchi ,  Shigeo Ohshima

    发明人： Kazuaki Kawaguchi ,  Shigeo Ohshima

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/4076

    摘要： In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.