公开(公告)号：US08853770B2

公开(公告)日：2014-10-07

申请号：US12724771

申请日：2010-03-16

申请人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

发明人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

IPC分类号： H01L29/76 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L29/407 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate and a second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover a portion of the termination structure oxide layer.

摘要翻译： 为功率晶体管提供终端结构。 端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。 具有第二类型的导电性的掺杂区域设置在终端沟槽下方的衬底中。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与栅极间隔开的部分MOS栅极向半导体衬底的边缘延伸。 端接结构氧化物层形成在覆盖MOS栅极的一部分并朝向衬底边缘延伸的端接沟槽上。 第一导电层形成在半导体衬底的背侧表面上，并且第二导电层形成在有源区顶部，MOS栅极的暴露部分之上，并延伸以覆盖端接结构氧化物层的一部分。

公开(公告)号：US08716794B2

公开(公告)日：2014-05-06

申请号：US13131779

申请日：2010-08-10

申请人： Xiaorong Luo ,  Florin Udrea

发明人： Xiaorong Luo ,  Florin Udrea

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7812

摘要： The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

摘要翻译： 本发明涉及半导体功率器件和功率集成电路（IC）。 本发明的横向SOI MOSFET包括延伸到电介质掩埋层的沟槽栅极，漂移区域中的一个或多个电介质沟槽以及所述电介质沟槽中的掩埋栅极。 电介质在所述电介质沟槽中的介电常数低于所述有源层的介电常数。 首先，所述电介质沟槽不仅大大提高了击穿电压，还降低了间距尺寸。 其次，沟槽栅极使垂直方向上的有效导电区域变宽。 第三，所述沟槽栅极和掩埋栅极的双栅极增加了沟道和电流密度。 从而，降低了特定导通电阻和功率损耗。 本发明的器件具有高电压，高速，低功耗，低成本，易集成等诸多优点。 本发明的器件特别适用于功率集成电路和RF功率集成电路。

公开(公告)号：US08564097B2

公开(公告)日：2013-10-22

申请号：US12760754

申请日：2010-04-15

申请人： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

发明人： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

IPC分类号： H01L27/082

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

摘要： An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.

摘要翻译： 提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域 所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。 提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域 并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。 这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。

公开(公告)号：US08432030B2

公开(公告)日：2013-04-30

申请号：US13171788

申请日：2011-06-29

申请人： Rajesh Kumar Malhan ,  C Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

发明人： Rajesh Kumar Malhan ,  C Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

IPC分类号： H01L23/48

CPC分类号： H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US08174069B2

公开(公告)日：2012-05-08

申请号：US12186231

申请日：2008-08-05

申请人： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

发明人： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

IPC分类号： H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0839 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7394 ,  H01L29/7824

摘要： A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

摘要翻译： 功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。 装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。 顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。 在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。 器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。 该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

公开(公告)号：US07968940B2

公开(公告)日：2011-06-28

申请号：US11863231

申请日：2007-09-27

申请人： Florin Udrea

发明人： Florin Udrea

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/66348 ,  H01L29/7396

摘要： Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n− drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

摘要翻译： 具有两个栅极的双栅极IGBT指的是其中第二栅极用于控制空穴电流的阴极。 在导通状态下，可以大大抑制空穴电流。 在切换期间，允许空穴电流流过第二通道。 结合具有预形成的空穴通道的耗尽型p沟道MOSFET，当0V或者低于特定阈值电压的正电压被施加在第二栅极和阴极之间时，其导通的电压不被用于p沟道栅极的负电压 。 通过增加n阱的掺杂和宽度降低碱运输因子，或者通过减少深阱的掺杂降低注入效率，提供通过积极收集的空穴量的主动控制。 器件至少包括阳极，阴极，半导体衬底，n-漂移区，第一和第二栅极，n +阴极区域; p +阴极短，深p阱，n阱和预形成的孔道。

公开(公告)号：US07849727B2

公开(公告)日：2010-12-14

申请号：US12065296

申请日：2006-07-12

申请人： Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

发明人： Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

IPC分类号： G01N7/00

CPC分类号： G01N33/0047 ,  G01N27/14 ,  G01N33/0031

摘要： A gas-sensing semiconductor device 1′ is fabricated on a silicon substrate 2′ having a thin silicon dioxide insulating layer 3′ in which a resistive heater 6 made of doped single crystal silicon formed simultaneously with source and drain regions of CMOS circuitry is embedded. The device 1′ includes a sensing area provided with a gas-sensitive layer 9′ separated from the heater 6′ by an insulating layer 4′. As one of the final fabrication steps, the substrate 2′ is back-etched so as to form a thin membrane in the sensing area. The heater 6′ has a generally circular-shaped structure surrounding a heat spreading plate 16′, and consists of two sets 20′, 21′ of meandering resistors having arcuate portions nested within one another and interconnected in labyrinthine form. The fabrication of the heater at the same time as the source and drain regions of CMOS circuitry is particularly advantageous in that the gas-sensing semiconductor device is produced without requiring any fabrication steps in addition to those already employed in the IC processing apart from a post-CMOS back etch and deposition of the gas-sensitive layer. The circular design is advantageous in that it is the best solution to minimise the size of the membrane at fixed power loss and heated area.

摘要翻译： 在具有薄的二氧化硅绝缘层3'的硅衬底2'上制造气体感测半导体器件1'，其中嵌入与CMOS电路的源极和漏极区域同时形成的由掺杂单晶硅制成的电阻加热器6。 装置1'包括具有通过绝缘层4'与加热器6'分离的气敏层9'的感测区域。 作为最终制造步骤之一，衬底2'被反蚀刻以在感测区域中形成薄膜。 加热器6'具有围绕散热板16'的大致圆形结构，并且由具有彼此嵌套并且以迷宫形式互连的弓形部分的曲折电阻器的两组20'，21'组成。 与CMOS电路的源极和漏极区域同时地制造加热器是特别有利的，因为除了在后处理中已经用于IC处理中的那些之外，制造气体感测半导体器件不需要任何制造步骤 -CMOS背蚀刻和气敏层的沉积。 圆形设计是有利的，因为它是在固定功率损耗和加热面积下最小化膜尺寸的最佳解决方案。

公开(公告)号：US20090126460A1

公开(公告)日：2009-05-21

申请号：US12065296

申请日：2006-07-12

申请人： Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

发明人： Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

IPC分类号： G01N7/00 ,  H01L29/78

CPC分类号： G01N33/0047 ,  G01N27/14 ,  G01N33/0031

摘要： A gas-sensing semiconductor device 1′ is fabricated on a silicon substrate 2′ having a thin silicon dioxide insulating layer 3′ in which a resistive heater 6 made of doped single crystal silicon formed simultaneously with source and drain regions of CMOS circuitry is embedded. The device 1′ includes a sensing area provided with a gas-sensitive layer 9′ separated from the heater 6′ by an insulating layer 4′. As one of the final fabrication steps, the substrate 2′ is back-etched so as to form a thin membrane in the sensing area. The heater 6′ has a generally circular-shaped structure surrounding a heat spreading plate 16′, and consists of two sets 20′, 21′ of meandering resistors having arcuate portions nested within one another and interconnected in labyrinthine form. The fabrication of the heater at the same time as the source and drain regions of CMOS circuitry is particularly advantageous in that the gas-sensing semiconductor device is produced without requiring any fabrication steps in addition to those already employed in the IC processing apart from a post-CMOS back etch and deposition of the gas-sensitive layer. The circular design is advantageous in that it is the best solution to minimise the size of the membrane at fixed power loss and heated area.

摘要翻译： 在具有薄的二氧化硅绝缘层3'的硅衬底2'上制造气体感测半导体器件1'，其中嵌入与CMOS电路的源极和漏极区域同时形成的由掺杂单晶硅制成的电阻加热器6。 装置1'包括具有通过绝缘层4'与加热器6'分离的气敏层9'的感测区域。 作为最终制造步骤之一，衬底2'被反蚀刻以在感测区域中形成薄膜。 加热器6'具有围绕散热板16'的大致圆形结构，并且由具有彼此嵌套并且以迷宫形式互连的弓形部分的曲折电阻器的两组20'，21'组成。 与CMOS电路的源极和漏极区域同时地制造加热器是特别有利的，因为除了在后处理中已经用于IC处理中的那些之外，制造气体感测半导体器件不需要任何制造步骤 -CMOS背蚀刻和气敏层的沉积。 圆形设计是有利的，因为它是在固定功率损耗和加热面积下最小化膜尺寸的最佳解决方案。

公开(公告)号：US07495300B2

公开(公告)日：2009-02-24

申请号：US11092654

申请日：2005-03-30

申请人： Julian William Gardner ,  James Anthony Covington ,  Florin Udrea

发明人： Julian William Gardner ,  James Anthony Covington ,  Florin Udrea

IPC分类号： H01L29/78

CPC分类号： G01N27/128

摘要： A gas-sensing semiconductor device is fabricated on a silicon substrate having a thin silicon oxide insulating layer in which a resistive heater made of a CMOS compatible high temperature metal is embedded. The high temperature metal is tungsten. The device includes at least one sensing area provided with a gas-sensitive layer separated from the heater by an insulating layer. As one of the final fabrication steps, the substrate is back-etched so as to form a thin membrane in the sensing area. Except for the back-etch and the gas-sensitive layer formation, that are carried out post-CMOS, all other layers, including the tungsten resistive heater, are made using a CMOS process employing tungsten metallisation. The device can be monolithically integrated with the drive, control and transducing circuitry using low cost CMOS processing. The heater, the insulating layer and other layers are made within the CMOS sequence and they do not require extra masks or processing.

摘要翻译： 气体感测半导体器件制造在具有薄的氧化硅绝缘层的硅衬底上，其中嵌入由CMOS兼容的高温金属制成的电阻加热器。 高温金属是钨。 该装置包括设置有通过绝缘层与加热器分离的气敏层的至少一个感测区域。 作为最终制造步骤之一，衬底被反蚀刻以在感测区域中形成薄膜。 除了在CMOS之后执行的背蚀刻和气敏层形成之外，包括钨电阻加热器在内的所有其它层均采用采用钨金属化的CMOS工艺制成。 该器件可以使用低成本CMOS处理与驱动器，控制和转换电路单片集成。 加热器，绝缘层和其他层是在CMOS序列内制成的，它们不需要额外的掩模或处理。

公开(公告)号：US07411272B2

公开(公告)日：2008-08-12

申请号：US11174605

申请日：2005-07-06

申请人： Florin Udrea ,  Gehan A. J. Amaratunga

发明人： Florin Udrea ,  Gehan A. J. Amaratunga

IPC分类号： H01L29/00

CPC分类号： H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

摘要翻译： 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。