公开(公告)号：US10367083B2

公开(公告)日：2019-07-30

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L21/762 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20190181250A1

公开(公告)日：2019-06-13

申请号：US16278268

申请日：2019-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/08 ,  H01L21/762 ,  H01L29/417 ,  H01L29/73 ,  H01L29/10 ,  H01L29/06

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20180175180A1

公开(公告)日：2018-06-21

申请号：US15383171

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  David L. Harame ,  Renata Camillo-Castillo

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/417 ,  H01L21/265 ,  H01L29/735 ,  H01L27/12

CPC classification number: H01L29/737 ,  H01L21/26513 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/735

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

公开(公告)号：US09799693B2

公开(公告)日：2017-10-24

申请号：US15215674

申请日：2016-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146 ,  H01L21/762 ,  H01L31/0232

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US09703036B2

公开(公告)日：2017-07-11

申请号：US15041103

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

公开(公告)号：US20170098699A1

公开(公告)日：2017-04-06

申请号：US14874039

申请日：2015-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  David L. Harame

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/04 ,  H01L21/762 ,  H01L21/225

CPC classification number: H01L29/732 ,  H01L21/76 ,  H01L21/762 ,  H01L29/0642 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.

公开(公告)号：US09543403B2

公开(公告)日：2017-01-10

申请号：US14601655

申请日：2015-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L29/00 ,  H01L29/66 ,  H01L21/306 ,  H01L29/73 ,  H01L29/08

CPC classification number: H01L29/66234 ,  H01L21/306 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.

Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 在基板上形成第一半导体层，在第一半导体层上形成第二半导体层。 蚀刻第一半导体层，第二半导体层和衬底以限定来自第二半导体层的第一和第二发射极指状物以及横向位于第一和第二发射极指之间的衬底中的沟槽。 第一半导体层可以用作器件结构中的基层。

公开(公告)号：US20160343759A1

公开(公告)日：2016-11-24

申请号：US15215674

申请日：2016-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US09496377B2

公开(公告)日：2016-11-15

申请号：US14747525

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Peng Cheng ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/73 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7371

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

公开(公告)号：US09437717B2

公开(公告)日：2016-09-06

申请号：US13971982

申请日：2013-08-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

IPC: H01L29/73 ,  H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  G06F17/50

CPC classification number: H01L29/73 ,  G06F17/5045 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371

Abstract: Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.