公开(公告)号：US09165837B1

公开(公告)日：2015-10-20

申请号：US14525743

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Murat Kerem Akarvardar ,  Ajey P. Jacob ,  Steven Bentley

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/823821 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3247 ,  H01L21/76224 ,  H01L21/823431

Abstract: Methods of forming a defect free heteroepitaxial replacement fin by annealing the sacrificial Si fin with H2 prior to STI formation are provided. Embodiments include forming a Si fin on a substrate; annealing the Si fin with H2; forming a STI layer around the annealed Si fin; annealing the STI layer; removing a portion of the annealed Si fin by etching, forming a recess; forming a replacement fin in the recess; and recessing the annealed STI layer to expose an active replacement fin.

Abstract translation: 提供了在STI形成之前通过用H 2退火牺牲Si翅片来形成无缺陷异质外延替换翅片的方法。 实施例包括在基板上形成Si翅片; 用H2退火Si翅片; 在退火的Si翅片周围形成STI层; 退火STI层; 通过蚀刻去除退火的Si翅片的一部分，形成凹部; 在凹槽中形成替换翅片; 并使退火的STI层凹陷以暴露活性替换翅片。

公开(公告)号：US08716156B1

公开(公告)日：2014-05-06

申请号：US13757069

申请日：2013-02-01

Applicant: GlobalFoundries Inc.

Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

IPC: H01L21/31

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成心轴结构，执行氧化过程以氧化心轴结构的至少一部分，从而在心轴结构上限定氧化区，去除氧化区，由此限定减少 厚度心轴结构，在厚度较小的心轴结构上形成多个翅片，并执行蚀刻工艺以选择性地移除至少一部分厚度较小的心轴结构，从而露出每个翅片的至少一部分。

公开(公告)号：US10685847B2

公开(公告)日：2020-06-16

申请号：US15598905

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/31 ,  H01L21/311 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8234

Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.

公开(公告)号：US20190326286A1

公开(公告)日：2019-10-24

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US20190148494A1

公开(公告)日：2019-05-16

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/24 ,  H01L21/8234

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US10269812B1

公开(公告)日：2019-04-23

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L27/112 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/24 ,  H01L29/78 ,  H01L29/808 ,  H01L45/00 ,  H01L29/66 ,  H01L29/06 ,  H01L23/522 ,  H01L21/02

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US10249710B2

公开(公告)日：2019-04-02

申请号：US15652873

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Deepak Nayak

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/10 ,  H01L29/16

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

公开(公告)号：US10186577B2

公开(公告)日：2019-01-22

申请号：US14477096

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/311

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.

公开(公告)号：US10157794B1

公开(公告)日：2018-12-18

申请号：US15626321

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet H. Suvarna ,  Steven Bentley ,  Mark V. Raymond ,  Peter M. Zeitzoff

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

公开(公告)号：US10141414B1

公开(公告)日：2018-11-27

申请号：US15784500

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78

Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.