公开(公告)号：US20190043577A1

公开(公告)日：2019-02-07

申请号：US16073902

申请日：2016-02-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0028 ,  G11C13/003 ,  G11C2013/0071 ,  G11C2013/0092 ,  G11C2213/79

Abstract: In one example in accordance with the present disclosure a memristive array is described. The memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.

公开(公告)号：US20190043573A1

公开(公告)日：2019-02-07

申请号：US16073922

申请日：2016-02-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/2297 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C29/50012 ,  G11C2013/0045 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.

公开(公告)号：US10169297B2

公开(公告)日：2019-01-01

申请号：US15500486

申请日：2015-04-16

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G06F17/16 ,  G11C7/10 ,  G11C13/00 ,  G06F7/544 ,  G06F7/50 ,  G06F7/523

Abstract: In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multiplication engines to perform a multiply operation by receiving a memory element output from a corresponding resistive memory element, receiving an input signal, and generating a multiplication output based on a received memory element output and a received input signal. The array also includes an accumulation engine to sum multiplication outputs from the number of multiplication engines.

公开(公告)号：US10026474B2

公开(公告)日：2018-07-17

申请号：US15116105

申请日：2014-04-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Switched memristor analog tuning employs a switch-selectable programmed resistance to tune a resistance-tunable analog circuit. A plurality of switched memristors is to provide the switch-selectable programmed resistance. The resistance-tunable analog circuit is connected to the plurality of switched memristors. The switch-selectable programmed resistance is to tune an analog attribute of the resistance-tunable analog circuit.

公开(公告)号：US09947397B2

公开(公告)日：2018-04-17

申请号：US15329776

申请日：2014-09-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Yoocharn Jeon

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/77

Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder includes a number of field effect transistor decoder switches corresponding to specific lines in a crosspoint array and a sense amplifier coupled to at least some of the field effect transistor decoder switches and includes a set of inference field effect transistors matched to the field effect transistor decoder switches to infer a stimulus voltage applied to a memory element in a crosspoint array.

公开(公告)号：US20180095748A1

公开(公告)日：2018-04-05

申请号：US15281280

申请日：2016-09-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Le Zheng

IPC: G06F9/30 ,  G06N3/04 ,  G06N3/063

CPC classification number: G06F9/3001 ,  G06F9/30 ,  G06N3/04 ,  G06N3/0635

Abstract: An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network.

公开(公告)号：US09847129B2

公开(公告)日：2017-12-19

申请号：US15324685

申请日：2014-07-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/52

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C27/00 ,  G11C29/52 ,  G11C29/70 ,  G11C29/785 ,  G11C2013/0092 ,  G11C2213/75

Abstract: Error reduction in memristor programming includes programming an n-th switched memristor of a switched memristor array with an error-corrected target resistance. The error-corrected target resistance is a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor. The n-th switched memristor programming is to reduce a total resistance error of the switched memristor array.

公开(公告)号：US09806736B2

公开(公告)日：2017-10-31

申请号：US15116095

申请日：2014-04-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: H03M1/00 ,  H03M1/80 ,  H03M1/78 ,  H01L45/00

CPC classification number: H03M1/808 ,  G11C2213/75 ,  H01L45/1253 ,  H01L45/145 ,  H03M1/78 ,  H03M1/785

Abstract: Switched memristor digital-to-analog conversion employs a set of switch-selectable programmed resistances corresponding to a digital-to-analog conversion mapping to convert a digital input into an analog output. The digital input is to establish an analog resistance of a plurality of switched memristors connected in series that are switch selectable. The plurality of switched memristors is to provide the set of switch-selectable programmed resistances in accordance with the digital-to-analog conversion mapping.

公开(公告)号：US20170287540A1

公开(公告)日：2017-10-05

申请号：US15507790

申请日：2014-09-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Amit S. Sharma ,  Gary Gibson ,  Erik Ordentlich ,  Naveen Muralimanohar

IPC: G11C8/10 ,  G11C13/00

CPC classification number: G11C8/10 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028

Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.

公开(公告)号：US20170206956A1

公开(公告)日：2017-07-20

申请号：US15325040

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin Foltin ,  Yoocharn Jeon ,  Brent Buchanan ,  Erik Ordentlich ,  Naveen Muralimanohar ,  James S. Ignowski ,  Jacquelyn M. Ingemi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/068

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.