公开(公告)号：US20060077713A1

公开(公告)日：2006-04-13

申请号：US11181721

申请日：2005-07-15

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US20060009502A1

公开(公告)日：2006-01-12

申请号：US11188275

申请日：2005-07-22

申请人： Masatsugu Horiuchi ,  Masaru Iwai ,  Toshio Sada ,  Makoto Mizuno

发明人： Masatsugu Horiuchi ,  Masaru Iwai ,  Toshio Sada ,  Makoto Mizuno

IPC分类号： A61K31/4184

CPC分类号： A61K31/4178 ,  A61K31/4422 ,  A61K31/455 ,  A61K45/06 ,  A61K2300/00

摘要： A pharmaceutical composition comprising the following active ingredients: (A) an angiotensin II receptor antagonist selected from the group of a compound having a formula (I), a pharmacologically acceptable ester thereof and a pharmacologically acceptable salt thereof (for example, olmesartan medoxomil); and (B) a calcium channel blocker selected from the group consisting of a 1,4-dihydropyridine compound and a pharmacologically acceptable salt thereof (for example, azelnidipine), for the prophylaxis and/or treatment of arteriosclerosis, hypertension, heart diseases, renal diseases or cerebrovascular diseases.

摘要翻译： 一种药物组合物，其包含以下活性成分：（A）选自具有式（I）的化合物，其药理学可接受的酯和其药理学可接受的盐（例如奥美沙坦酯）的血管紧张素II受体拮抗剂; 和（B）选自由1,4-二氢吡啶化合物及其药理学上可接受的盐（例如，azelnidipine）组成的组的钙通道阻滞剂，用于预防和/或治疗动脉硬化，高血压，心脏病，肾脏 疾病或脑血管疾病。

公开(公告)号：US06726594B2

公开(公告)日：2004-04-27

申请号：US10198994

申请日：2002-07-22

申请人： Makoto Mizuno ,  Kazuhisa Mogi

发明人： Makoto Mizuno ,  Kazuhisa Mogi

IPC分类号： B60K4112

CPC分类号： B60W10/06 ,  B60W10/04 ,  B60W10/101 ,  B60W30/1819 ,  B60W30/1882 ,  F16H61/66 ,  F16H2302/02 ,  F16H2306/30 ,  Y10T477/619 ,  Y10T477/623

摘要： A control system for a vehicle in which an internal combustion engine whose output torque is controlled based on a required output power is coupled to a continuously variable transmission whose input rotation speed is controlled based on the required output power. A controller of the system determines a final target operating point of the engine which is defined by the output torque and the input rotation speed, on the basis of the required output power, and sets a transient operating point to one of possible operating points that can be achieved within a predetermined period of time such that the operating point of the engine approaches the final target operating point. The controller then controls the output torque and the input rotation speed of the continuously variable transmission so as to operate the engine at the set transient operating point.

摘要翻译： 一种用于车辆的控制系统，其中输出扭矩基于所需输出功率被控制的内燃机被耦合到基于所需输出功率来控制输入转速的无级变速器。 该系统的控制器基于所需的输出功率来确定由输出转矩和输入转速定义的发动机的最终目标工作点，并将瞬时工作点设置为可以工作点之一 在预定时间段内实现，使得发动机的操作点接近最终目标操作点。 然后，控制器控制无级变速器的输出转矩和输入转速，以便在设定的瞬时工作点操作发动机。

公开(公告)号：US5888900A

公开(公告)日：1999-03-30

申请号：US901697

申请日：1997-07-28

申请人： Makoto Mizuno ,  Toshihiro Shimizu ,  Masaaki Fujishima ,  Koji Hanihara ,  Itaru Tsuchiya ,  Yasuo Yagi

发明人： Makoto Mizuno ,  Toshihiro Shimizu ,  Masaaki Fujishima ,  Koji Hanihara ,  Itaru Tsuchiya ,  Yasuo Yagi

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/31053 ,  H01L21/76819 ,  Y10S438/926

摘要： A method for manufacturing semiconductor device is provided, this method comprises the steps of: depositing a metal film for forming wirings on a substrate; forming a wiring layer, wherein dummy wiring is inserted between wiring space where the dummy wiring can be inserted, and wiring space, where the dummy wiring cannot be inserted, is reduced by widening wiring pattern facing the wiring space; forming an interlayer insulating film on said wiring layer; and flattening surface of the interlayer insulating film. The film can be flattened by a CMP method or by an etchback of entire surface of the film. It is possible to flatten the surface of the semiconductor device cost-effectively and precisely.

摘要翻译： 提供一种制造半导体器件的方法，该方法包括以下步骤：在衬底上沉积用于形成布线的金属膜; 形成布线层，其中虚拟布线插入在可插入虚拟布线的布线空间之间，并且通过加宽面向布线空间的布线图案来减少虚拟布线不能插入的布线空间; 在所述布线层上形成层间绝缘膜; 和层间绝缘膜的平坦化表面。 该膜可以通过CMP方法或通过膜的整个表面的回蚀而变平。 可以经济高效地精确地使半导体器件的表面平坦化。

公开(公告)号：US5845848A

公开(公告)日：1998-12-08

申请号：US887438

申请日：1997-07-02

申请人： Kiyoo Amako ,  Makoto Mizuno

发明人： Kiyoo Amako ,  Makoto Mizuno

IPC分类号： B64F5/00 ,  F02C6/00 ,  F02C6/08 ,  F02C6/18 ,  F02G5/02 ,  G05D23/00 ,  B05B1/24 ,  B64D15/10

CPC分类号： B64F5/0054 ,  B64F5/0063

摘要： A deicer includes a water tank storing water and an antifreeze solution tank storing an antifreeze solution. The water tank and the antifreeze solution tank are provided with heat exchangers, respectively. Pumps are further provided for feeding the water and the antifreeze solution in the respective tanks to a spray nozzle for spraying out a mixture of the water and the antifreeze solution. A gas turbine is provided for driving the foregoing pumps. Exhaust gas of the gas turbine is introduced into the heat exchangers through a control of valve switching so as to hold temperatures of the water and the antifreeze solution in the respective tanks to be constant. Further, bleed air of the gas turbine is fed to an air nozzle so as to be jetted out therefrom.

摘要翻译： 除冰机包括储存水的水箱和储存防冻溶液的防冻溶液罐。 水箱和防冻液箱分别设有热交换器。 进一步提供泵将各个罐中的水和防冻溶液供给到用于喷射水和防冻溶液的混合物的喷嘴。 提供用于驱动上述泵的燃气轮机。 燃气轮机的废气通过阀切换的控制被引入热交换器，从而将各水箱中的水和防冻液的温度保持恒定。 此外，燃气轮机的排气被供给到空气喷嘴以从其喷出。

公开(公告)号：US08054680B2

公开(公告)日：2011-11-08

申请号：US10852150

申请日：2004-05-25

申请人： Nozomu Matsuzaki ,  Tetsuya Ishimaru ,  Makoto Mizuno ,  Takashi Hashimoto

发明人： Nozomu Matsuzaki ,  Tetsuya Ishimaru ,  Makoto Mizuno ,  Takashi Hashimoto

IPC分类号： G11C11/34 ,  G11C7/00 ,  H01L29/792

CPC分类号： G11C16/107 ,  G11C16/3468

摘要： Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.

摘要翻译： 通过从基板注入电子并将电子提取到栅极电极进行擦除和写入操作的存储单元构成半导体非易失性存储器件。 这是一个栅极提取半导体非易失性存储器件。 在该器件中，如果在擦除和写入操作的第一过程中施加擦除偏置，则发生过度过热状态的存储器单元，并且这种存储器单元的电荷保留特性降低。 本发明提供一种半导体非易失性存储器件，其使用在施加擦除偏置之前将所有存储单元写入擦除单元的装置，然后施加擦除偏置。

公开(公告)号：US07972920B2

公开(公告)日：2011-07-05

申请号：US12700344

申请日：2010-02-04

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/8244 ,  G11C11/40

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US07859773B2

公开(公告)日：2010-12-28

申请号：US12029539

申请日：2008-02-12

申请人： Makoto Mizuno ,  Ichiro Onuki

发明人： Makoto Mizuno ,  Ichiro Onuki

IPC分类号： G02B7/02

CPC分类号： G02B7/023 ,  G02B7/005 ,  G03F7/70258 ,  G03F7/70825

摘要： An optical-element driving mechanism is configured to drive an optical element, and includes a uniaxial driving mechanism that includes a linear actuator that drives in a first direction, and a link mechanism that converts a displacement in a direction orthogonal to the first direction. The linear actuator is level with the link mechanism in an optical-axis direction. The uniaxial driving mechanism is arranged in order of the link mechanism and the linear actuator in a radial direction when viewed form an optical axis of the optical element.

摘要翻译： 光学元件驱动机构被配置为驱动光学元件，并且包括单轴驱动机构，该单轴驱动机构包括沿第一方向驱动的线性致动器和连接机构，该连杆机构转换与第一方向正交的方向的位移。 线性致动器与链接机构在光轴方向上平齐。 当从光学元件的光轴观察时，单轴驱动机构按照连杆机构和线性致动器的径向方向排列。

公开(公告)号：US20100321803A1

公开(公告)日：2010-12-23

申请号：US12870877

申请日：2010-08-30

申请人： Ryo Nawata ,  Makoto Mizuno ,  Shigeyuki Uzawa

发明人： Ryo Nawata ,  Makoto Mizuno ,  Shigeyuki Uzawa

IPC分类号： G02B7/00

CPC分类号： G02B7/005 ,  G02B7/1827 ,  G03F7/70258 ,  G03F7/70825

摘要： An optical element is moved in six-degrees-of-freedom. Three first displacement sensors are disposed on a base plate and measure respective displacement amounts of three mutually different points on the optical element in a first direction. A second displacement sensor measures a displacement amount of one point on the optical element in a second direction. Two third displacement sensors measure respective displacement amounts of two mutually different points on the optical element in a third direction. A transformation processor transforms the six measured displacement amounts A calibration processor calibrates the transformed displacement amounts with a calibration matrix of which coefficients are previously obtained to calibrate the displacement amounts in the six-degrees-of-freedom, which have errors due to measurement errors of the displacement sensors. A controller outputs command values based on differences between the calibrated displacement amounts and target displacement amounts.

摘要翻译： 光学元件以6自由度移动。 三个第一位移传感器设置在基板上，并且在第一方向上测量光学元件上的三个相互不同的点的相应位移量。 第二位移传感器在第二方向上测量光学元件上的一个点的位移量。 两个第三位移传感器在第三方向测量光学元件上的两个相互不同的点的相应位移量。 变换处理器转换六个测量的位移量A校准处理器用先前获得的系数的校准矩阵校准变换的位移量，以校准六自由度中的位移量，其由于测量误差而发生错误 位移传感器。 控制器基于校准的位移量和目标位移量之间的差异输出命令值。

公开(公告)号：US07848177B2

公开(公告)日：2010-12-07

申请号：US12269098

申请日：2008-11-12

申请人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行管线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。