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51.发明公开公开(公告)号：US20240264657A1
公开(公告)日：2024-08-08
申请号：US18601001
申请日：2024-03-11
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
IPC: G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/36
CPC classification number: G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/363 , G09G5/366 , G09G2310/066 , G09G2310/08 , G09G2340/02 , G09G2360/06 , G09G2360/08 , G09G2370/022 , G09G2370/16
Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
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公开(公告)号：US11733758B2
公开(公告)日：2023-08-22
申请号：US17411878
申请日：2021-08-25
Applicant: INTEL CORPORATION
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
IPC: G09G3/00 , G06F1/3209 , H04W52/02 , G06F1/324 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/07 , G06F11/30 , H04M1/72448
CPC classification number: G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/0781 , G06F11/3062 , H04W52/0258 , H04M1/72448 , Y02D10/00 , Y02D30/70
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20220206853A1
公开(公告)日：2022-06-30
申请号：US17520583
申请日：2021-11-05
Applicant: Intel Corporation
Inventor： Abhishek R Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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54.发明申请公开(公告)号：US20220197362A1
公开(公告)日：2022-06-23
申请号：US17517090
申请日：2021-11-02
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
IPC: G06F1/3234 , G06F1/324 , G06F1/3237 , G06F1/3296 , G09G5/36
Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
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公开(公告)号：US11169850B2
公开(公告)日：2021-11-09
申请号：US16726341
申请日：2019-12-24
Applicant: Intel Corporation
Inventor： Abhishek R Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US20210065779A1
公开(公告)日：2021-03-04
申请号：US17018071
申请日：2020-09-11
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhishek R. Appu
IPC: G11C11/4094 , G06F13/40 , G06F9/38 , G06F9/30 , G06F12/0897 , G06F12/0868 , G06F12/109 , G06F12/1027 , G06F3/06 , G11C11/4074 , G11C11/4093 , G06F12/08
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US10790010B2
公开(公告)日：2020-09-29
申请号：US16435878
申请日：2019-06-10
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC: G11C7/00 , G11C11/4094 , G06F13/40 , G06F9/38 , G06F9/30 , G06F12/0897 , G06F12/0868 , G06F12/109 , G06F12/1027 , G06F3/06 , G11C11/4074 , G11C11/4093 , G06F12/08 , G11C11/419
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US20200272215A1
公开(公告)日：2020-08-27
申请号：US16805480
申请日：2020-02-28
Applicant: INTEL CORPORATION
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
IPC: G06F1/3209 , H04W52/02 , G06F1/324 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/07 , G06F11/30
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10580104B2
公开(公告)日：2020-03-03
申请号：US15488723
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Kamal Sinha , Bhushan M. Borole , Altug Koker , Joydeep Ray , Wenyin Fu
IPC: G06F13/372 , G06T1/20 , G06F3/06 , G06T11/00 , G06T1/60
Abstract: Power for on-die heavily used local memories in general purpose graphics processing unit (GPGPU) applications may be reduced by using low latency read and high latency write operations. Power consumption in read heavy graphic operations can be reduced using a small memory footprint design with possible reduction of hot spotting in some embodiments.
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公开(公告)号：US20200019207A1
公开(公告)日：2020-01-16
申请号：US16527165
申请日：2019-07-31
Applicant: Intel Corporation
Inventor： Iqbal R. Rajwani , Altug Koker , Bhushan M. Borole , Kamal Sinha , Abhishek R. Appu , Anupama A. Thaploo , Sunil Nekkanti , Wenyin Fu
Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.
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