公开(公告)号：US20180285268A1

公开(公告)日：2018-10-04

申请号：US15475197

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kunal Kishore Korgaonkar ,  Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/40

Abstract: In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the idle indicator has been set, identify a first cache line to be evicted from a first set of cache lines of the mid-level cache and send a request to write the first cache line to the LLC.

公开(公告)号：US10062731B2

公开(公告)日：2018-08-28

申请号：US15523324

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03K19/20 ,  H01L27/22 ,  H03K19/18 ,  H03K19/173

CPC classification number: H01L27/22 ,  H01L43/00 ,  H03K19/173 ,  H03K19/18

Abstract: An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.

公开(公告)号：US20180240583A1

公开(公告)日：2018-08-23

申请号：US15751111

申请日：2015-09-09

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H03K19/18 ,  H01L43/12 ,  H01F41/32

CPC classification number: H01F10/3254 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/32 ,  H01L27/228 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/18 ,  H03K19/23

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).

公开(公告)号：US20180232311A1

公开(公告)日：2018-08-16

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0831 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F13/1642 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US20170352802A1

公开(公告)日：2017-12-07

申请号：US15525521

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Dmitri Nikonov ,  Sasikanth Manipatruni ,  Ian Young

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/10 ,  H01L41/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/22 ,  G11C21/00 ,  H01L41/12 ,  H01L43/10 ,  H03K19/18 ,  H03K19/23

Abstract: Described is an interconnect which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a second magnetoelectric material layer coupled to the ferromagnetic layer, wherein the ferromagnetic layer extends from the first end to the second end. Described is a majority gate device which comprises: a ferromagnetic layer; and first, second, third, and fourth magnetoelectric material layers coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a tunnel junction device coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first terminal coupled to a tunneling junction device; a second terminal coupled to a layer coupling the tunneling junction device and a magnetoelectric device; and a third terminal coupled to the magnetoelectric device.

公开(公告)号：US09620188B2

公开(公告)日：2017-04-11

申请号：US14780489

申请日：2013-06-21

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/18 ,  H01L43/08 ,  H01L27/22 ,  H01L43/06 ,  H01L43/12

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/226 ,  H01L27/228 ,  H01L43/06 ,  H01L43/08 ,  H01L43/12

Abstract: An apparatus is described having a select line and an interconnect with Spin Hall Effect (SHE) material. The interconnect is coupled to a write bit line. A transistor is coupled to the select line and the interconnect. The transistor is controllable by a word line. The apparatus also includes an MTJ device having a free magnetic layer coupled to the interconnect.

公开(公告)号：US09559698B2

公开(公告)日：2017-01-31

申请号：US14906025

申请日：2013-09-30

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Michael Kishinevsky ,  Ian A. Young

IPC: H03K19/16 ,  H01L29/66 ,  G11C11/16 ,  H03K19/18 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: H03K19/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08 ,  H03K19/18

Abstract: An embodiment includes a C-element logic gate implemented as a spin logic device that provides a compact and low-power implementation of asynchronous logic by implementing a C-element with spintronic technology. An embodiment includes a first nanopillar including a first contact and a first fixed magnetic layer; a second nanopillar including a second contact and a second fixed magnetic layer; and a third nanopillar including a third contact, a tunnel barrier, and a third fixed magnetic layer; wherein (a) the first, second, and third nanopillars are all formed over a free magnetic layer, and (b) the third fixed magnetic layer, the tunnel barrier, and the free magnetic layer form a magnetic tunnel junction (MTJ). Other embodiments are described herein.

Abstract translation: 实施例包括被实现为自旋逻辑器件的C元件逻辑门，其通过使用自旋电子技术实现C元件来提供异步逻辑的紧凑和低功率实施。 一个实施例包括第一纳米柱，其包括第一接触和第一固定磁性层; 包括第二接触和第二固定磁性层的第二纳米柱; 以及包括第三接触件，隧道势垒和第三固定磁性层的第三纳米柱; 其中（a）第一，第二和第三纳米锥都形成在自由磁性层上，并且（b）第三固定磁性层，隧道势垒和自由磁性层形成磁性隧道结（MTJ）。 本文描述了其它实施例。

公开(公告)号：US09294035B2

公开(公告)日：2016-03-22

申请号：US13994714

申请日：2013-03-28

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Raseong Kim ,  Rajashree Baskaran ,  Rajeev K. Dokania ,  Ian A. Young

IPC: H03B5/12 ,  H03B5/30 ,  H01L29/66 ,  H01L29/78

CPC classification number: H03B5/30 ,  H01L29/66795 ,  H01L29/7831 ,  H01L2924/13067 ,  H01L2924/13084

Abstract: An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.

Abstract translation: 实施例包括：振荡器，包括形成在基板上的放大器; 形成在所述衬底上的多栅极共振沟道阵列包括：（a）包括鳍片的晶体管，每个鳍片在源极和漏极节点之间具有耦合到共源极和漏极触点的沟道; 和（b）共同的第一和第二三栅极，其耦合到每个散热片并且位于源极和漏极接触之间; 其中当第一和第二三门中的一个被周期性地激活以在翅片上产生周期性向下的力时，翅片以第一频率机械共振。 其他实施例包括在源极和漏极节点之间具有沟道的非平面晶体管和鳍上的三栅极; 其中当所述第一三栅极被周期性地激活以在所述散热片上产生周期性向下的力时，所述翅片机械谐振。 本文描述了其它实施例。

公开(公告)号：US12009018B2

公开(公告)日：2024-06-11

申请号：US17839345

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Benjamin Buford ,  Kaan Oguz ,  John J. Plombon ,  Ian A. Young

IPC: G11C11/16 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10N50/80 ,  H10N50/85

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

公开(公告)号：US11665975B2

公开(公告)日：2023-05-30

申请号：US16012673

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Sasikanth Manipatruni ,  Ian Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01L27/22

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/329 ,  H01F10/3254 ,  H01F10/3286 ,  H01L27/224 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12 ,  H01F10/3272

Abstract: An apparatus is provided which comprises: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; and a first device (e.g., a selector device) coupled at one end of the interconnect and to the second word-line; and a second device coupled to the magnetic junction, the first word-line and the source-line.