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    Memory including a perovskite material
    51.
    发明授权
    Memory including a perovskite material 有权

    公开(公告)号：US10861861B2

    公开(公告)日：2020-12-08

    申请号：US16221083

    申请日：2018-12-14

    Applicant: Intel Corporation

    Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Sou-Chi Chang ,  Uygar E. Avci ,  Ian A. Young

    IPC: H01L27/11509 ,  H01L27/11592

    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.

    Ferroelectric based memory cell with non-volatile retention
    54.
    发明授权
    Ferroelectric based memory cell with non-volatile retention 有权

    公开(公告)号：US10573385B2

    公开(公告)日：2020-02-25

    申请号：US15567942

    申请日：2015-05-28

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C5/02 ,  G11C14/00 ,  G11C11/22 ,  H01L27/11502

    Abstract: Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.

    Transistors with temperature compensating gate structures
    55.
    发明授权
    Transistors with temperature compensating gate structures 有权

    公开(公告)号：US10553694B2

    公开(公告)日：2020-02-04

    申请号：US16474874

    申请日：2017-04-11

    Applicant: INTEL CORPORATION

    Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

    Abstract: Techniques are disclosed for forming semiconductor integrated circuits including a channel region, a gate dielectric between the gate electrode and the channel region, a first layer between the gate dielectric and the gate electrode, the first layer comprising temperature compensation material. In addition, the integrate circuit includes a source region adjacent to the channel region, a source metal contact on the source region, a drain region adjacent to the channel region, and a drain metal contact on the drain region. The temperature compensation material has a temperature dependent band structure, work-function, or polarization that dynamically adjusts the threshold voltage of the transistor in response to increased operating temperature to maintain the off-state current Ioff stable or otherwise within an acceptable tolerance. The temperature compensation material may be used in conjunction with a work function material to help provide desired performance at lower or non-elevated temperatures.

    Isolation structures for an integrated circuit element and method of making same
    57.
    发明授权
    Isolation structures for an integrated circuit element and method of making same 有权

    公开(公告)号：US10468489B2

    公开(公告)日：2019-11-05

    申请号：US15747719

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Aaron D. Lilak ,  Uygar E. Avci ,  David L. Kencke ,  Patrick Morrow ,  Kerryann Foley ,  Stephen M. Cea ,  Rishabh Mehandru

    IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

    Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.

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