公开(公告)号：US20230206112A1

公开(公告)日：2023-06-29

申请号：US17563575

申请日：2021-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Julian Timothy Dolby

IPC: G06N20/00 ,  G03F1/70

CPC classification number: G06N20/00 ,  G03F1/70

Abstract: A computer-implemented method is provided for creating a photolithographic mask. The method includes, in a model building stage, obtaining lithography polygon coordinates from an input lithography target layout. The method further includes, in the model building stage, obtaining mask polygon coordinates from an input mask layout from a test mask. The method also includes, in the model building stage, obtaining correlated mask to lithography features from the lithography polygon coordinates and the mask polygon coordinates. The method additionally includes, in the model building stage, performing linear regression on the correlated mask to lithography features to obtain a machine learning model for predicting an output mask from an input lithography target design. The method further includes, in an inference stage, predicting a given output mask from a given input lithography target design using the machine learning model.

公开(公告)号：US20220190167A1

公开(公告)日：2022-06-16

申请号：US17118752

申请日：2020-12-11

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  REINALDO VEGA ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/07

Abstract: A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer.

公开(公告)号：US20220173312A1

公开(公告)日：2022-06-02

申请号：US17106286

申请日：2020-11-30

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Anirban Chandra ,  Takashi Ando ,  Cheng Chi ,  Reinaldo Vega

IPC: H01L45/00

Abstract: A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.

公开(公告)号：US20220158091A1

公开(公告)日：2022-05-19

申请号：US16952203

申请日：2020-11-19

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Praneet Adusumilli ,  REINALDO VEGA ,  Cheng Chi

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/04 ,  G06N3/063

Abstract: A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode, a first resistive structure in contact with the first electrode, a dielectric layer in contact with the first resistive structure, and a second resistive structure in contact with the dielectric layer. The second resistive structure includes a resistive material layer and a high work function metal core. The ReRAM device also includes a second electrode in contact with the second resistive structure.

公开(公告)号：US20200343342A1

公开(公告)日：2020-10-29

申请号：US16397541

申请日：2019-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chi-Chun Liu ,  Cheng Chi ,  Kangguo Cheng

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308

Abstract: Semiconductor devices and methods of forming the same include forming spacers on respective sidewalls above a stack of alternating channel layers and sacrificial layers, leaving an opening between the spacers. The stack is etched, between the spacers, to form a central opening in the stack that separates the channel layers into respective pairs of channel structures. The sacrificial material is etched away to expose top and bottom surfaces of the channel structures. A gate stack is formed on, between, and around the channel structures, including in the central opening between pairs of channel structures.

公开(公告)号：US20200027983A1

公开(公告)日：2020-01-23

申请号：US16039472

申请日：2018-07-19

Applicant: International Business Machines Corporation

Inventor： Steven Bentley ,  Cheng Chi ,  Chanro Park ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

Abstract: Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion.

公开(公告)号：US10475660B2

公开(公告)日：2019-11-12

申请号：US15363607

申请日：2016-11-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/30 ,  H01L21/31 ,  H01L21/82 ,  H01L21/762 ,  H01L29/06 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/027 ,  H01L21/033

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US10418485B2

公开(公告)日：2019-09-17

申请号：US16046178

申请日：2018-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US10361315B1

公开(公告)日：2019-07-23

申请号：US15928325

申请日：2018-03-22

Applicant: International Business Machines Corporation

Inventor： Chun-Chen Yeh ,  Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Cheng Chi ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/8238

Abstract: Fabricating a semiconductor device includes receiving a semiconductor structure including a substrate, a fin formed on a portion of the substrate, and a first hard mask disposed on a top surface of the fin. A bottom spacer is formed on the substrate in contact with a bottom portion of the fin. A top spacer is formed in contact with a top portion of the fin. A lateral recess is formed in the substrate under the bottom spacer. A first epitaxy upon the bottom spacer within the lateral recess and a second epitaxy upon the top spacer are simultaneously grown. The first epitaxy forms a bottom source and drain and the second epitaxy forms a top source and drain.

公开(公告)号：US20190140052A1

公开(公告)日：2019-05-09

申请号：US16233825

申请日：2018-12-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.