公开(公告)号：US20220336627A1

公开(公告)日：2022-10-20

申请号：US17811129

申请日：2022-07-07

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Christopher J. Waskiewicz ,  Shahab Siddiqui ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the invention are directed to a semiconductor device that includes a channel fin; a trench adjacent to an upper region of the channel fin; and an oxygen-blocking layer within the trench. The oxygen-blocking layer includes an oxygen gettering material configured to remove oxygen from an environment to which the oxygen-blocking layer is exposed.

公开(公告)号：US11476346B2

公开(公告)日：2022-10-18

申请号：US16910296

申请日：2020-06-24

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Christopher J. Waskiewicz ,  Shahab Siddiqui ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a top spacer trench adjacent to an upper region of the channel fin. An oxygen-blocking layer is deposited within the top spacer trench and over the upper region of the channel fin. A top spacer is formed within the top spacer trench and over a portion of the oxygen-blocking layer that is within the top spacer trench. The oxygen-blocking layer includes an oxygen gettering material.

公开(公告)号：US20220059696A1

公开(公告)日：2022-02-24

申请号：US17516994

申请日：2021-11-02

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Ruilong Xie ,  Jay William Strane ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.

公开(公告)号：US11239165B2

公开(公告)日：2022-02-01

申请号：US16814305

申请日：2020-03-10

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Christopher J. Waskiewicz ,  Kangguo Cheng ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L23/528

Abstract: Interconnect structures and methods for forming the interconnect structures generally include forming a bulk metal encapsulated in first and second interlayer dielectrics, a liner layer about a lower surface of the bulk metal and a metal cap layer about an upper surface of the bulk metal. The liner layer is in the first interlayer dielectric and the metal cap layer is in the second interlayer dielectric, wherein liner layer and the metal cap layer are different metals.

公开(公告)号：US20220020688A1

公开(公告)日：2022-01-20

申请号：US16932731

申请日：2020-07-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Christopher J. Waskiewicz ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Ashim DUTTA

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A fully aligned via interconnect structure and techniques for formation thereof using subtractive metal patterning are provided. In one aspect, an interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; and at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx, wherein a top surface of at least one of the metal lines Mx−1 has a stepped profile. In another aspect, another interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx; and sidewall spacers alongside the metal lines Mx. A method of forming an interconnect structure is also provided.

公开(公告)号：US11171051B1

公开(公告)日：2021-11-09

申请号：US16867757

申请日：2020-05-06

Applicant: International Business Machines Corporation

Inventor： Jennifer Fullam ,  Su Chen Fan ,  Christopher J. Waskiewicz ,  Muthumanickam Sankarapandian

IPC: H01L21/768 ,  H01L23/522

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

公开(公告)号：US20210328041A1

公开(公告)日：2021-10-21

申请号：US16849072

申请日：2020-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Indira Seshadri ,  Su Chen Fan ,  Christopher J. Waskiewicz ,  Eric Miller

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L29/78 ,  H01L21/28

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

公开(公告)号：US10741652B2

公开(公告)日：2020-08-11

申请号：US16569739

申请日：2019-09-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Christopher J. Waskiewicz ,  Alexander Reznicek ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.

公开(公告)号：US10741452B2

公开(公告)日：2020-08-11

申请号：US16173378

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/033 ,  H01L29/66 ,  H01L27/088

Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US20200081746A1

公开(公告)日：2020-03-12

申请号：US16125466

申请日：2018-09-07

Applicant: International Business Machines Corporation

Inventor： Jonathan Fry ,  Christopher J. Penny ,  Marc Bergendahl ,  Christopher J. Waskiewicz ,  Jean Wynne ,  James Demarest

IPC: G06F9/50 ,  H04L9/06 ,  G06F9/48

Abstract: An example operation may include one or more of connecting, by a load leveler, to a blockchain network comprising a plurality of nodes and configured to store a common work item, computing, by the load leveler, loads across the plurality of the nodes that need to execute the common work item upon completion of current tasks, determining, by the load leveler, a network load impact based on execution of a common blockchain consensus checking process on the network nodes, executing, by the load leveler, a work assessment process based on the loads computed across the plurality of the nodes and on the determined network load impact of the blockchain network, and assigning, by the load leveler, new tasks to the nodes based on results of the execution of the work assessment process.