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公开(公告)号：US20190189452A1
公开(公告)日：2019-06-20
申请号：US15845652
申请日：2017-12-18
摘要： The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
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52.发明授权公开(公告)号：US10276452B1
公开(公告)日：2019-04-30
申请号：US15867834
申请日：2018-01-11
发明人： Indira Seshadri , Ekmini Anuja De Silva , Jing Guo , Romain J. Lallement , Ruqiang Bao , Zhenxing Bi , Sivananda Kanakasabapathy
IPC分类号： H01L21/8238 , H01L21/308 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/78
摘要： A method of forming a semiconductor structure includes forming first and second stacked nanosheet channel structures on a semiconductor substrate, with each nanosheet channel structure including a plurality of stacked channel regions interspersed with sacrificial regions. In a resulting semiconductor structure, an N-type stacked nanosheet channel structure is formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure is formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures includes a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
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公开(公告)号：US12021135B2
公开(公告)日：2024-06-25
申请号：US18314850
申请日：2023-05-10
发明人： Tao Li , Indira Seshadri , Nelson Felix , Eric Miller
IPC分类号： H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/823814 , H01L21/823885 , H01L27/092 , H01L29/0653 , H01L29/0847 , H01L29/7827
摘要： A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.
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公开(公告)号：US20240178292A1
公开(公告)日：2024-05-30
申请号：US17994487
申请日：2022-11-28
IPC分类号： H01L29/423 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/775
CPC分类号： H01L29/42392 , H01L27/088 , H01L29/0673 , H01L29/41775 , H01L29/66553 , H01L29/775
摘要： A semiconductor structure is presented including semiconductor layers of a first nanosheet stack, semiconductor layers of a second nanosheet stack formed over and having a stepped nanosheet formation with respect to the semiconductor layers of the first nanosheet stack, a first epitaxial growth formed adjacent the semiconductor layers of the first nanosheet stack, and a second epitaxial growth formed adjacent the semiconductor layers of the second nanosheet stack such that the second epitaxial growth has a stepped formation with respect to the first epitaxial growth. The second epitaxial growth has a volume greater than a volume of the first epitaxial growth.
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公开(公告)号：US20240072035A1
公开(公告)日：2024-02-29
申请号：US17900203
申请日：2022-08-31
发明人： Ruilong Xie , Indira Seshadri , Cheng Chi , Albert M. Chu
IPC分类号： H01L27/02 , H01L27/118
CPC分类号： H01L27/0207 , H01L27/11807 , H01L2027/11866
摘要： A circuit is presented including a plurality of cells separated by a plurality of cell boundaries and at least one curved gate cut region disposed over a curved cell boundary of the plurality of cell boundaries. The at least one curved gate cut region separates a reduced active area from a widened active area. The reduced active area is defined above the curved cell boundary and the widened active area is defined below the curved cell boundary.
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公开(公告)号：US11756961B2
公开(公告)日：2023-09-12
申请号：US17584801
申请日：2022-01-26
发明人： Tsung-Sheng Kang , Tao Li , Ardasheir Rahman , Praveen Joseph , Indira Seshadri , Ekmini Anuja De Silva
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238 , H01L29/06 , H01L29/78 , H01L21/02 , H01L29/66
CPC分类号： H01L27/0922 , H01L21/02238 , H01L21/02255 , H01L21/823807 , H01L21/823885 , H01L27/1207 , H01L29/0676 , H01L29/66666 , H01L29/7827
摘要： A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.
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公开(公告)号：US11500293B2
公开(公告)日：2022-11-15
申请号：US16657654
申请日：2019-10-18
发明人： Ekmini Anuja De Silva , Indira Seshadri , Jing Guo , Ashim Dutta , Nelson Felix
IPC分类号： G03F7/20 , H01L21/308 , H01L21/027 , G03F1/22 , H01L21/033 , G03F1/54 , G03F7/40
摘要： A semiconductor structure comprises a semiconductor substrate, and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack comprises at least a hard mask layer and a resist layer formed over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on a developed pattern of the resist layer through inclusion in the hard mask layer of one or more materials inhibiting deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer. The hard mask layer illustratively comprises, for example, at least one of a grafted self-assembled monolayer configured to inhibit deposition of the metal-containing layer, and a grafted polymer brush material configured to inhibit deposition of the metal-containing layer.
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公开(公告)号：US11121024B2
公开(公告)日：2021-09-14
申请号：US16542502
申请日：2019-08-16
IPC分类号： H01L21/762 , H01L23/544 , H01L21/027 , H01L21/768 , H01L21/48 , B82Y40/00
摘要： A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.
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公开(公告)号：US20210118743A1
公开(公告)日：2021-04-22
申请号：US17138834
申请日：2020-12-30
发明人： Romain Lallement , Indira Seshadri , Ruqiang Bao
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/02 , H01L29/06 , H01L27/092
摘要： Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.
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公开(公告)号：US10903124B2
公开(公告)日：2021-01-26
申请号：US16399864
申请日：2019-04-30
发明人： Romain Lallement , Indira Seshadri , Ruqiang Bao
IPC分类号： H01L21/70 , H01L21/8234 , H01L21/28 , H01L21/02 , H01L29/06 , H01L27/092
摘要： Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.
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