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    MEASURING INDIVIDUAL DEVICE DEGRADATION IN CMOS CIRCUITS
    51.
    发明申请
    MEASURING INDIVIDUAL DEVICE DEGRADATION IN CMOS CIRCUITS 审中-公开
    测量CMOS电路中的个性化设备降级

    公开(公告)号：US20170059644A1

    公开(公告)日：2017-03-02

    申请号：US14843280

    申请日：2015-09-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Barry P. Linder ,  Keith A. Jenkins

    IPC: G01R31/26

    CPC classification number: G01R31/2621 ,  G01R31/2642 ,  G01R31/2884

    Abstract: Methods and systems for measuring degradation includes measuring an initial electrical characteristic of a test device in a ring oscillator that includes multiple oscillator stages, each having a delay stage and one or more fan-out devices, and a test stage having a delay stage and the test device. The ring oscillator is operated for a period of time. The electrical characteristic of the test device is measured after operating the ring oscillator. A level of degradation in the test device is determined using a processor based on the measurements of the electrical characteristic of the test device.

    Abstract translation: 用于测量劣化的方法和系统包括测量包括多个振荡器级的环形振荡器中的测试装置的初始电特性，每个具有延迟级和一个或多个扇出装置，以及具有延迟级的测试级和 测试设备。 环形振荡器运行一段时间。 在操作环形振荡器之后测量测试装置的电气特性。 使用基于测试装置的电气特性的测量的处理器来确定测试装置的劣化程度。

    MEASUREMENT FOR TRANSISTOR OUTPUT CHARACTERISTICS WITH AND WITHOUT SELF HEATING
    53.
    发明申请
    MEASUREMENT FOR TRANSISTOR OUTPUT CHARACTERISTICS WITH AND WITHOUT SELF HEATING 有权
    具有和不具有自加热功能的晶体管输出特性的测量

    公开(公告)号：US20160266196A1

    公开(公告)日：2016-09-15

    申请号：US14747546

    申请日：2015-06-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Keith A. Jenkins ,  Barry P. Linder

    IPC: G01R31/26 ,  G01R31/02

    CPC classification number: G01R31/2628 ,  G01R31/025 ,  G01R31/2601 ,  G01R31/2648

    Abstract: A method of measuring semiconductor output characteristics is provided that includes connecting a pulse generator to the gate structure of a semiconductor device, and applying a plurality of voltage pulses at least some of which having a different pulse width to the gate structure of the semiconductor device. The average current is measured from the drain structure of the device for a duration of each pulse of the plurality of pulses. From the measured values for the average current, a self-heating curve of the average current divided by the pulse width is plotted as a function of the pulse width. The self-heating curve is then extrapolated to a pulse width substantially equal to zero to provide a value of drain current measurements without self-heating effects.

    Abstract translation: 提供了一种测量半导体输出特性的方法，包括将脉冲发生器连接到半导体器件的栅极结构，并将至少其中一些具有不同脉冲宽度的电压脉冲施加到半导体器件的栅极结构。 在多个脉冲的每个脉冲的持续时间内，从器件的漏极结构测量平均电流。 根据平均电流的测量值，将平均电流的自加热曲线除以脉冲宽度作为脉冲宽度的函数。 然后将自热曲线外推到基本上等于零的脉冲宽度，以提供没有自热效应的漏极电流测量值。

    TEST STRUCTURE TO MEASURE DELAY VARIABILITY MISMATCH OF DIGITAL LOGIC PATHS
    54.
    发明申请
    TEST STRUCTURE TO MEASURE DELAY VARIABILITY MISMATCH OF DIGITAL LOGIC PATHS 有权
    测量数字逻辑时间延迟误差的测试结构

    公开(公告)号：US20160209467A1

    公开(公告)日：2016-07-21

    申请号：US15001373

    申请日：2016-01-20

    Applicant: International Business Machines Corporation

    Inventor： Karthik Balakrishnan ,  Bruce M. Fleischer ,  Keith A. Jenkins ,  Christos Vezyrtzis

    IPC: G01R31/3177 ,  G01R31/28

    CPC classification number: G01R31/2884 ,  G01R31/31726

    Abstract: An integrated circuit includes a test block which in turn includes a plurality of identical paths; a counter selectively coupled to the plurality of identical paths to selectively obtain a count of at least one of correctly operating paths and incorrectly operating paths from each of the plurality of identical paths; and a plurality of count latches selectively coupled to the counter to store output of the counter. Each path in turn includes a first clocked latch; a clocked logic path beginning and ending at the first clocked latch; and a clocked detection circuit coupled to the first clocked latch and the counter, which determines whether the clocked logic path is operating properly in a given clock period.

    Abstract translation: 集成电路包括测试块，测试块又包括多个相同的路径; 选择性地耦合到所述多个相同路径的计数器，以选择性地获得来自所述多个相同路径中的每一个的正确操作路径和错误地操作路径中的至少一个的计数; 以及选择性地耦合到计数器以存储计数器的输出的多个计数锁存器。 每个路径依次包括第一时钟锁存器; 在第一时钟锁存器处开始和结束的时钟逻辑路径; 以及耦合到第一时钟锁存器和计数器的时钟检测电路，其确定时钟逻辑路径在给定时钟周期内是否正常工作。

    Dynamic predictor of semiconductor lifetime limits
    55.
    发明授权
    Dynamic predictor of semiconductor lifetime limits 有权

    公开(公告)号：US10746785B2

    公开(公告)日：2020-08-18

    申请号：US15230067

    申请日：2016-08-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chen-Yong Cher ,  Keith A. Jenkins ,  Barry P. Linder

    IPC: G01R31/28

    Abstract: A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

    Analytics to determine customer satisfaction
    56.
    发明授权
    Analytics to determine customer satisfaction 审中-公开

    公开(公告)号：US10671958B2

    公开(公告)日：2020-06-02

    申请号：US16406157

    申请日：2019-05-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Karthik Balakrishnan ,  Keith A. Jenkins ,  Barry P. Linder

    IPC: G06Q10/06 ,  G06K9/00 ,  G06K9/62

    Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.

    MEASURING INDIVIDUAL DEVICE DEGRADATION IN CMOS CIRCUITS
    59.
    发明申请
    MEASURING INDIVIDUAL DEVICE DEGRADATION IN CMOS CIRCUITS 审中-公开

    公开(公告)号：US20180364296A1

    公开(公告)日：2018-12-20

    申请号：US16110275

    申请日：2018-08-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Barry P. Linder ,  Keith A. Jenkins

    IPC: G01R31/26 ,  G01R31/28

    Abstract: Methods and systems for measuring degradation includes measuring an initial electrical characteristic of a test device in a ring oscillator that includes multiple oscillator stages and a test stage having a delay stage and the test device. The ring oscillator is operated for a period of time. The electrical characteristic of the test device is measured after operating the ring oscillator. A level of degradation in the test device is determined using a processor based on the measurements of the electrical characteristic of the test device.

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