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    Fabrication of semiconductors with high-K/metal gate electrodes
    51.
    发明授权
    Fabrication of semiconductors with high-K/metal gate electrodes 有权
    具有高K /金属栅电极的半导体制造

    公开(公告)号：US08445964B2

    公开(公告)日：2013-05-21

    申请号：US13349883

    申请日：2012-01-13

    Applicant: Rohit Pal ,  Stephan Waidmann

    Inventor： Rohit Pal ,  Stephan Waidmann

    IPC: H01L21/02

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

    Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

    Abstract translation: 具有高K /金属栅极的半导体器件由间隔物形成，其具有基本上抵抗后续蚀刻以去除上覆间隔物，从而避免替换并增加制造生产量。 实施例包括在衬底（例如SOI衬底）上形成具有上表面和侧表面的高K /金属栅极，并且在高K /金属栅极的侧表面上依次形成第一间隔物 不同于第一间隔物的材料的非氧化物材料，第二间隔物和与第二间隔物不同的材料的第三间隔物。 在形成源极和漏极区域，例如外延生长的硅 - 锗之后，用蚀刻剂（例如热磷酸）蚀刻第三间隔物，第二间隔物基本上抵抗其上，从而避免更换。

    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION
    52.
    发明申请
    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION 有权
    高K金属电极结构由早期盖层适应形成

    公开(公告)号：US20130034942A1

    公开(公告)日：2013-02-07

    申请号：US13565970

    申请日：2012-08-03

    Applicant: Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    Inventor： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    IPC: H01L21/336

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

    Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

    Abstract translation: 当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性 栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。 在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是 在暴露观察者电极材料的表面时实现。

    Formation of a Channel Semiconductor Alloy by a Nitride Hard Mask Layer and an Oxide Mask
    54.
    发明申请
    Formation of a Channel Semiconductor Alloy by a Nitride Hard Mask Layer and an Oxide Mask 有权
    通过氮化物硬掩模层和氧化物掩模形成沟道半导体合金

    公开(公告)号：US20120156864A1

    公开(公告)日：2012-06-21

    申请号：US13197387

    申请日：2011-08-03

    Applicant: Stephan Kronholz ,  Rohit Pal

    Inventor： Stephan Kronholz ,  Rohit Pal

    IPC: H01L21/8234

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

    Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.

    Abstract translation: 当形成复杂的高k金属栅电极结构时，可以通过基于硬掩模方式生长阈值调节半导体合金来增强器件特性的均匀性，这可能导致不太显着的表面形貌，特别是在密集 包装设备区域。 为此，在一些说明性实施例中，沉积的硬掩模材料可用于选择性地提供厚度减小和均匀性优异的氧化物掩模。

    GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE
    56.
    发明申请
    GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE 有权
    通过硅掺杂物轮廓变化进行GATE蚀刻优化

    公开(公告)号：US20120119308A1

    公开(公告)日：2012-05-17

    申请号：US13353013

    申请日：2012-01-18

    Applicant: Man Fai NG ,  Rohit Pal

    Inventor： Man Fai NG ,  Rohit Pal

    IPC: H01L29/772

    CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

    Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

    Abstract translation: 包括金属栅电极的改进的半导体器件通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度而形成，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
    58.
    发明授权
    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
    用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法

    公开(公告)号：US07932143B1

    公开(公告)日：2011-04-26

    申请号：US12604281

    申请日：2009-10-22

    Applicant: Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

    Inventor： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

    IPC: H01L21/8238

    CPC classification number: H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

    Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

    Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

    Methods for fabricating MOS devices having highly stressed channels
    59.
    发明授权
    Methods for fabricating MOS devices having highly stressed channels 有权
    制造具有高应力通道的MOS器件的方法

    公开(公告)号：US07767534B2

    公开(公告)日：2010-08-03

    申请号：US12240682

    申请日：2008-09-29

    Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

    Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

    IPC: H01L21/336

    CPC classification number: H01L29/7847 ,  H01L29/66636

    Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

    Abstract translation: 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，沉积覆盖栅电极的应力诱导层，退火含硅衬底以重结晶 栅电极，去除应力诱导层，使用栅电极作为蚀刻掩模蚀刻到衬底中的凹槽，以及在凹槽中外延生长杂质掺杂的含硅区域。

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