公开(公告)号：US20200006204A1

公开(公告)日：2020-01-02

申请号：US16423715

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H01L23/498 ,  H05K1/18 ,  H05K1/14 ,  H05K3/46 ,  H05K3/36 ,  H01L23/538

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

公开(公告)号：US10403604B2

公开(公告)日：2019-09-03

申请号：US15766150

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Ping Ping Ooi ,  Kooi Chi Ooi ,  Shanggar Periaman

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50

Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

公开(公告)号：US20190229057A1

公开(公告)日：2019-07-25

申请号：US16329080

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L23/538 ,  H01L25/065

Abstract: A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.

公开(公告)号：US10354957B2

公开(公告)日：2019-07-16

申请号：US15778379

申请日：2015-11-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Stephen Harvey Hall ,  Khang Choong Yong ,  Kooi Chi Ooi ,  Eric C Gantner

IPC: H01L23/495 ,  H01L23/538 ,  H05K1/02 ,  H01L21/56 ,  H01L23/66 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H05K1/18

Abstract: An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.

公开(公告)号：US20190045625A1

公开(公告)日：2019-02-07

申请号：US15841880

申请日：2017-12-14

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Yun Ling ,  Chia Voon Tan

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: Techniques and mechanisms for mitigating the effect of signal noise on communication via an interconnect. In an embodiment, a substrate includes an interconnect and a conductor which has a hole formed therein. Portions of the interconnect variously extend over a side of the conductor, wherein another recess portion of the interconnect extends from a plane which includes the side, and further extends at least partially into the hole. The configuration of the recess portion extending within the hole may contribute to an impedance which dampens a transmitter slew rate of the communication. In an embodiment, a total distance along a path formed by the interconnect is equal to or less than 5.5 inches.

公开(公告)号：US10153253B2

公开(公告)日：2018-12-11

申请号：US15357233

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H05K1/11 ,  H05K3/30 ,  H05K3/36 ,  H05K1/14

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

公开(公告)号：US10085342B2

公开(公告)日：2018-09-25

申请号：US15376872

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim ,  Chin Lee Kuan ,  Howe Yin Loo

IPC: H01L21/00 ,  H01L23/48 ,  H05K1/16 ,  H01F17/02 ,  H01F17/00 ,  H01F41/04 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H05K1/165 ,  H01F17/0033 ,  H01F41/046 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19042 ,  H05K2201/086

Abstract: A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.

公开(公告)号：US10083922B2

公开(公告)日：2018-09-25

申请号：US15359926

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Chin Lee Kuan ,  Eng Huat Goh ,  Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

公开(公告)号：US20180226357A1

公开(公告)日：2018-08-09

申请号：US15889471

申请日：2018-02-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Paik Wen Ong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K3/4038 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package is disclosed. The semiconductor package includes a multilayer package substrate. The layers of the multi-layer substrate include one or more conductive layers to transmit information within the semiconductor package. The layers also include one or more conductive power supply layers to provide power to the semiconductor package and to one or more connected components. The layers also include one or more layers of dielectric material forming a substrate core dielectric. The layers also include an embedded reference plane within the substrate core dielectric, wherein the embedded reference plane is conductive and reduces electrical interference between the other conductive layers in the multilayer package substrate.

公开(公告)号：US20180168043A1

公开(公告)日：2018-06-14

申请号：US15376872

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim ,  Chin Lee Kuan ,  Howe Yin Loo

IPC: H05K1/16 ,  H01F17/02 ,  H01F17/00 ,  H01F41/04 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/046 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19042 ,  H05K2201/086

Abstract: A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.